Patents by Inventor Janos Fucsko
Janos Fucsko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8586483Abstract: A method of removing a metal nitride material is disclosed. The method comprises forming a semiconductor device structure comprising an exposed metal material and an exposed metal nitride material. The semiconductor device structure is subjected to a solution comprising water, ozone, and at least one additive to remove the exposed metal nitride material at a substantially greater rate than the exposed metal material. Resulting semiconductor device structures are also disclosed, as are compositions used to form the semiconductor device structures.Type: GrantFiled: September 11, 2012Date of Patent: November 19, 2013Assignee: Micron Technology, Inc.Inventors: Sanjeev Sapra, Janos Fucsko
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Publication number: 20130302995Abstract: Some embodiments include methods of treating semiconductor substrates. The substrates may be exposed to one or more conditions that vary continuously. The conditions may include temperature gradients, concentration gradients of one or more compositions that quench etchant, pH gradients to assist in removing particles, and/or concentration gradients of one or more compositions that assist in removing particles. The continuously varying conditions may be imparted by placing the semiconductor substrates in a bath of flowing rinsing solution, with the bath having at least two feed lines that provide the rinsing solution therein. One of the feed lines may be at a first condition, and the other may be at a second condition that is different from the first condition. The relative amount of rinsing solution provided to the bath by each feed line may be varied to continuously vary the condition within the bath.Type: ApplicationFiled: July 22, 2013Publication date: November 14, 2013Applicant: Micron Technology, Inc.Inventors: Janos Fucsko, Niraj B. Rana, Sandra Tagg, Robert J. Hanson, Gundu M. Sabde, Donald L. Yates, Patrick M. Flynn, Prashant Raghu, Kyle Grant
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Publication number: 20130295726Abstract: Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.Type: ApplicationFiled: July 10, 2013Publication date: November 7, 2013Inventors: Sanh D. Tang, Janos Fucsko
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Patent number: 8575040Abstract: Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane material to a silicon oxide layer.Type: GrantFiled: July 6, 2009Date of Patent: November 5, 2013Assignee: Micron Technology, Inc.Inventors: Janos Fucsko, John A. Smythe, III, Li Li, Grady S. Waldo
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Patent number: 8513064Abstract: Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.Type: GrantFiled: September 7, 2012Date of Patent: August 20, 2013Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Janos Fucsko
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Patent number: 8492288Abstract: Some embodiments include methods of treating semiconductor substrates. The substrates may be exposed to one or more conditions that vary continuously. The conditions may include temperature gradients, concentration gradients of one or more compositions that quench etchant, pH gradients to assist in removing particles, and/or concentration gradients of one or more compositions that assist in removing particles. The continuously varying conditions may be imparted by placing the semiconductor substrates in a bath of flowing rinsing solution, with the bath having at least two feed lines that provide the rinsing solution therein. One of the feed lines may be at a first condition, and the other may be at a second condition that is different from the first condition. The relative amount of rinsing solution provided to the bath by each feed line may be varied to continuously vary the condition within the bath.Type: GrantFiled: June 10, 2008Date of Patent: July 23, 2013Assignee: Micron Technology, Inc.Inventors: Janos Fucsko, Niraj B. Rana, Sandra Tagg, Robert J. Hanson, Gundu M. Sabde, Donald L. Yates, Patrick M. Flynn, Prashant Raghu, Kyle Grant
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Patent number: 8450214Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.Type: GrantFiled: August 30, 2012Date of Patent: May 28, 2013Assignee: Micron Technology, Inc.Inventors: Whonchee Lee, Janos Fucsko, David H. Wells
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Publication number: 20130009310Abstract: A method of removing a metal nitride material is disclosed. The method comprises forming a semiconductor device structure comprising an exposed metal material and an exposed metal nitride material. The semiconductor device structure is subjected to a solution comprising water, ozone, and at least one additive to remove the exposed metal nitride material at a substantially greater rate than the exposed metal material. Resulting semiconductor device structures are also disclosed, as are compositions used to form the semiconductor device structures.Type: ApplicationFiled: September 11, 2012Publication date: January 10, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Sanjeev Sapra, Janos Fucsko
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Publication number: 20120329215Abstract: Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.Type: ApplicationFiled: September 7, 2012Publication date: December 27, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Sanh D. Tang, Janos Fucsko
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Publication number: 20120322263Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.Type: ApplicationFiled: August 30, 2012Publication date: December 20, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Whonchee Lee, Janos Fucsko, David H. Wells
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Patent number: 8294246Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.Type: GrantFiled: July 5, 2011Date of Patent: October 23, 2012Assignee: Micron Technology, Inc.Inventors: Whonchee Lee, Janos Fucsko, David H. Wells
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Patent number: 8288213Abstract: Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.Type: GrantFiled: March 13, 2012Date of Patent: October 16, 2012Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Janos Fucsko
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Patent number: 8283259Abstract: A method of removing a metal nitride material is disclosed. The method comprises forming a semiconductor device structure comprising an exposed metal material and an exposed metal nitride material. The semiconductor device structure is subjected to a solution comprising water, ozone, and at least one additive to remove the exposed metal nitride material at a substantially greater rate than the exposed metal material.Type: GrantFiled: August 31, 2010Date of Patent: October 9, 2012Assignee: Micron Technology, Inc.Inventors: Sanjeev Sapra, Janos Fucsko
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Publication number: 20120178221Abstract: Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.Type: ApplicationFiled: March 13, 2012Publication date: July 12, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Sanh D. Tang, Janos Fucsko
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Publication number: 20120168898Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.Type: ApplicationFiled: March 9, 2012Publication date: July 5, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Janos Fucsko, David H. Wells, Patrick Flynn, Whonchee Lee
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Patent number: 8159050Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.Type: GrantFiled: January 14, 2010Date of Patent: April 17, 2012Assignee: Micron Technology, Inc.Inventors: Janos Fucsko, David H. Wells, Patrick Flynn, Whonchee Lee
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Patent number: 8158967Abstract: Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.Type: GrantFiled: November 23, 2009Date of Patent: April 17, 2012Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Janos Fucsko
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Publication number: 20120052678Abstract: A method of removing a metal nitride material is disclosed. The method comprises forming a semiconductor device structure comprising an exposed metal material and an exposed metal nitride material. The semiconductor device structure is subjected to a solution comprising water, ozone, and at least one additive to remove the exposed metal nitride material at a substantially greater rate than the exposed metal material.Type: ApplicationFiled: August 31, 2010Publication date: March 1, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Sanjeev Sapra, Janos Fucsko
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Patent number: 8124545Abstract: The invention includes methods in which one or more components of a carboxylic acid having an aqueous acidic dissociation constant of at least 1×10?6 are utilized during the etch of oxide (such as silicon dioxide or doped silicon dioxide). Two or more carboxylic acids can be utilized. Exemplary carboxylic acids include trichloroacetic acid, maleic acid, and citric acid.Type: GrantFiled: May 11, 2010Date of Patent: February 28, 2012Assignee: Micron Technology, Inc.Inventors: Niraj B. Rana, Kevin R. Shea, Janos Fucsko
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Publication number: 20110260298Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.Type: ApplicationFiled: July 5, 2011Publication date: October 27, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Whonchee Lee, Janos Fucsko, David H. Wells