Abstract: A middle-range (mid) low dropout (LDO) voltage has both sinking and sourcing current capability. The mid LDO can provide a voltage reference in active mode and power mode for core only design to work in a Safe Operating Area (SOA). The output of mid LDO can track IO power and/or core power dynamically. The mid LDO can comprise a voltage reference generator and a power-down controller connected to an amplifier, which output is connected to a decoupling capacitor. The provision of a high ground signal allows the mid LDO provide the sinking and sourcing currents.

Abstract: An IC device includes first and second resistors. The first resistor includes first and second metal segments extending in a first direction in a first metal layer, and a third metal segment extending in a second direction in a second metal layer, and electrically connecting the first and second metal segments. The second resistor includes fourth and fifth metal segments extending in the first direction in the first metal layer, and a sixth metal segment extending in the second direction in a third metal layer, and electrically connecting the fourth and fifth metal segments. The fourth and fifth metal segment have a width greater than a width of the first and second metal segments, the fourth metal segment is between the first and second metal segments and separated from the first metal segment by a distance, and a fourth and fifth metal segment separation is greater than the distance.

Abstract: A circuit for parameter PSRR measurement includes a filter, a first regulator and a second regulator. The filter may be configured for receiving an AC input signal and a DC input signal, and for outputting a combined output signal according to the AC input signal and the DC input signal. The first regulator may be configured for receiving the combined output signal, and for outputting a first output signal having a first AC component signal and a first DC component signal. The second regulator may be configured for receiving the first output signal, and for outputting a second output signal having a second AC component signal and a second DC component signal. A parameter PSRR of the second regulator may be obtained according to a ratio between the second AC component signal and the first AC component signal.

Abstract: One aspect of this description relates to a convolutional neural network (CNN). The CNN includes a memory cell array including a plurality of memory cells. Each memory cell includes at least one first capacitive element of a plurality of first capacitive elements. Each memory cell is configured to multiply a weight bit and an input bit to generate a product. The at least one first capacitive element is enabled when the product satisfies a predetermined threshold. The CNN includes a reference cell array including a plurality of second capacitive elements. The CNN includes a memory controller configured to compare a first signal associated with the plurality of first capacitive elements with a second signal associated with at least one second capacitive element of the plurality of second capacitive elements, and, based on the comparison, determine whether the at least one first capacitive element is enabled.

Abstract: In some embodiments, an integrated circuit device includes multiple rows of functional cells, with each row having a cell height. At least one of rows of functional cells includes at least one digital low-dropout voltage regulator (DLVR) cell with the cell height for the row. The DLVR cell includes: an input terminal, an output terminal, a voltage supply terminal, a reference voltage terminal, and one or more pairs of transistors. Each pair of transistors are arranged in cascode configuration connected between the voltage supply terminal and output terminal. The gate of one of the transistors the cascode configuration is connected to the input terminal, and the gate of the other transistor in the cascode configuration is connected to the reference voltage terminal. The four terminals each comprises a metal track in the bottom metal layer and disposed within the cell height.

Abstract: A semiconductor device includes an edge active cell, an inner active cell and a middle active cell. The edge active cell is located near an edge of the semiconductor device. The edge active cell includes a plurality of fingers. The inner active cell is adjacent to the edge active cell toward a central portion of the semiconductor device. The inner active cell includes a plurality of fingers and at least one of the plurality of fingers of the edge active cell is electrically connected to at least one of the plurality of fingers of the inner active cell. The middle active cell is located near the central portion of the semiconductor device. The middle active cell includes a plurality of fingers and each of the fingers of the middle active cell is electrically connected to each other.

Abstract: A middle-range (mid) low dropout (LDO) voltage has both sinking and sourcing current capability. The mid LDO can provide a voltage reference in active mode and power mode for core only design to work in a Safe Operating Area (SOA). The output of mid LDO can track TO power and/or core power dynamically. The mid LDO can comprise a voltage reference generator and a power-down controller connected to an amplifier, which output is connected to a decoupling capacitor. The provision of a high ground signal allows the mid LDO provide the sinking and sourcing currents.

Abstract: A method includes implanting a first dopant having a first dopant type into a substrate to define a plurality of source/drain (S/D) regions. The method further includes implanting a second dopant having the first dopant type into the substrate to define a channel region between adjacent S/D regions of the plurality of S/D regions, wherein a dopant concentration of the second dopant in the channel region is less than half of a dopant concentration of the first dopant in each of the plurality of S/D regions. The method further includes forming a gate stack over the channel region. The method further includes electrically coupling each of the plurality of S/D regions together.

Abstract: A circuit for parameter PSRR measurement includes a filter, a first regulator and a second regulator. The filter may be configured for receiving an AC input signal and a DC input signal, and for outputting a combined output signal according to the AC input signal and the DC input signal. The first regulator may be configured for receiving the combined output signal, and for outputting a first output signal having a first AC component signal and a first DC component signal. The second regulator may be configured for receiving the first output signal, and for outputting a second output signal having a second AC component signal and a second DC component signal. A parameter PSRR of the second regulator may be obtained according to a ratio between the second AC component signal and the first AC component signal.

Abstract: Disclosed herein are related to a system and a method of amplifying an input voltage based on cascaded charge pump boosting. In one aspect, first electrical charges are stored at a first capacitor according to the input voltage to obtain a second voltage. In one aspect, the second voltage is amplified according to the first electrical charges stored by the first capacitor to obtain a third voltage. In one aspect, second electrical charges are stored at the second capacitor according to the third voltage. In one aspect, the third voltage is amplified according to the second electrical charges stored by the second capacitor to obtain a fourth voltage.

Abstract: One aspect of this description relates to a convolutional neural network (CNN). The CNN includes a memory cell array including a plurality of memory cells. Each memory cell includes at least one first capacitive element of a plurality of first capacitive elements. Each memory cell is configured to multiply a weight bit and an input bit to generate a product. The at least one first capacitive element is enabled when the product satisfies a predetermined threshold. The CNN includes a reference cell array including a plurality of second capacitive elements. The CNN includes a memory controller configured to compare a first signal associated with the plurality of first capacitive elements with a second signal associated with at least one second capacitive element of the plurality of second capacitive elements, and, based on the comparison, determine whether the at least one first capacitive element is enabled.

Abstract: A device is provided. The device includes an operational amplifier, an output circuit, a first capacitor, and a second capacitor. The operational amplifier is configured to generate an output according to a feedback signal. The output circuit is configured to generate a first current signal in response to a supply voltage and the output of the operational amplifier. The first current signal includes a first ripple signal. The first capacitor and the second capacitor are coupled in parallel between the operational amplifier and the output circuit. The first capacitor is configured to receive the first current signal and feedback to the operational amplifier the first ripple signal.

Abstract: Disclosed herein are related to a method of amplifying an input voltage based on cascaded charge pump boosting. The method includes generating, at a set of capacitors, an input voltage corresponding to input data. The method further includes storing, by a first capacitor, first electrical charges corresponding to the input voltage to obtain a second voltage. The method further includes amplifying, a voltage amplifier, the second voltage according to the first electrical charges stored by the first capacitor to obtain a third voltage. The method further includes storing, by a second capacitor, second electrical charges according to the third voltage. The method further includes amplifying, by the voltage amplifier, the third voltage according to the second electrical charges stored by the second capacitor to obtain a fourth voltage.

Abstract: A method of operating a circuit includes providing the circuit, the circuit includes an operational amplifier, a plurality of sampling switches, a plurality of holding switches, and a plurality of combined switches. The method further includes: during a first phase, causing the plurality of sampling switches to be closed, the plurality of the holding switches to be open, and the plurality of combined switches to be open; during a second phase, causing the plurality of combined switches to be closed; during a third phase, causing the plurality of sampling switches to be open, the plurality of the holding switches to be closed, and the plurality of combined switches to be open; and during a fourth phase, causing the plurality of sampling switches to be open, the plurality of the holding switches to be closed, and the plurality of combined switches to be closed.

Abstract: A temperature sensor circuit, a control circuit, and a control method are provided. The temperature sensor circuit comprises a temperature sensor and a control circuit. The control circuit is coupled to the temperature sensor and comprises a current source, a sampling circuit, and a computing circuit. The current source is configured to provide a first current and a second current to the temperature sensor in different time periods. The sampling circuit is coupled to the temperature sensor and configured to obtain and store a first voltage information and a second voltage information from the temperature sensor when the first current and second current are respectively provided. The computing circuit is coupled to the sampling circuit and configured to generate a sensing result corresponding to a difference of subtracting the second voltage information from the first voltage information.

Abstract: A method includes implanting a first dopant having a first dopant type into a substrate to define a plurality of source/drain (S/D) regions. The method further includes implanting a second dopant having the first dopant type into the substrate to define a channel region between adjacent S/D regions of the plurality of S/D regions, wherein a dopant concentration of the second dopant in the channel region is less than half of a dopant concentration of the first dopant in each of the plurality of S/D regions. The method further includes forming a gate stack over the channel region. The method further includes electrically coupling each of the plurality of S/D regions together.

Abstract: Disclosed herein are related to a memory system including a memory cell and a circuit to operate the memory cell. In one aspect, the circuit includes a pair of transistors to electrically couple, to the bit line, a selected one of i) a voltage source to supply a reference voltage to the memory cell or ii) a sensor to sense a current through the memory cell. In one aspect, the circuit includes a first transistor. The first transistor and the bit line may be electrically coupled between the pair of transistors and the memory cell in series.

Abstract: Systems and methods are provided for generating a temperature compensated reference voltage. A temperature compensation circuit may include a proportional-to-absolute temperature (PTAT) circuit, and a complementary-to-absolute temperature (CTAT) circuit, with the PTAT circuit and the CTAT circuit including at least one common metal-oxide-semiconductor field-effect transistor (MOSFET) and being configured to collectively generate a reference voltage in response to a regulated current input. The PTAT circuit may be configured to produce an increase in magnitude of the reference voltage with an increase of temperature, and the CTAT circuit may be configured to generated a decrease in magnitude of the reference voltage with the increase of temperature, wherein the increase in magnitude of the reference voltage produced by the PTAT circuit is at least partially offset by the decrease in magnitude of the reference voltage produced by the CTAT circuit.

Abstract: A noise detecting circuit including an amplifier circuit amplifying an input signal indicating a noise level of a circuit to be detected and output an amplified signal; a filtering circuit receiving and filtering the amplified signal and output a filtered signal; and a comparing circuit receiving and compare the filtered signal to a reference voltage and output an output signal; wherein the filtering circuit includes: an output terminal; and a first filter selectively coupled to the output terminal, including: a sub-output terminal; a switch selectively coupling the sub-output terminal to the output terminal; a resistor, wherein a terminal of the resistor is coupled to the amplifier circuit and another terminal of the resistor is coupled to the sub-output terminal; and a capacitor, wherein a terminal of the capacitor is coupled to the sub-output terminal and another terminal of the capacitor is coupled to a reference voltage source.

Abstract: An integrated circuit includes a first circuit with m first units coupled in parallel, any of the first units including one or more first transistors coupled in series, and a second circuit with n second units coupled in parallel, any of the second units including one or more second transistors coupled in series. A gate terminal of the first circuit is coupled to a gate terminal of the second circuit. M and n are different positive integers.