Abstract: A trimmable resistor circuit and a method for operating the trimmable resistor circuit are provided. The trimmable resistor circuit includes first sources/drains and first gate structures alternatively arranged in a first row, second sources/drains and second gate structures alternatively arranged in a second row, third sources/drains and third gate structures alternatively arranged in a third row, first resistors disposed between the first row and the second row, and second resistors disposed between the second row and the third row. In the method for operating the trimmable resistor circuit, the first gate structures in the first row and the third gate structures in the third row are turned on. Then, the second gate structures in the second row are turned on/off according to a predetermined resistance value.

Abstract: A semiconductor device includes a substrate and a plurality of source/drain (S/D) regions in the substrate, wherein each of the plurality of S/D regions includes a first dopant having a first dopant type, and the each of the plurality of S/D regions are electrically coupled together. The semiconductor device further includes a gate stack over the substrate. The semiconductor device further includes a channel region in the substrate, wherein the channel region is below the gate stack and between adjacent S/D regions of the plurality of S/D regions, the channel region includes a second dopant having the first dopant type, and a concentration of the second dopant in the channel region is less than a concentration of the first dopant in each of the plurality of S/D regions.

Abstract: In a compute-in-memory (“CIM”) system, current signals, indicative of the result of a multiply-and-accumulate operation, from a CIM memory circuit are computed by comparing them with reference currents, which are generated by a current digital-to-analog converter (“DAC”) circuit. The memory circuit can include non-volatile memory (“NVM”) elements, which can be multi-level or two-level NVM elements. The characteristic sizes of the memory elements can be binary weighted to correspond to the respective place values in a multi-bit weight and/or a multi-bit input signal. Alternatively, NVM elements of equal size can be used to drive transistors of binary weighted sizes. The current comparison operation can be carried out at higher speeds than voltage computation. In some embodiments, simple clock-gated switches are used to produce even currents in the current summing branches. The clock-gated switches also serve to limit the time the cell currents are on, thereby reducing static power consumption.

Abstract: A method of calibrating a thermal sensor device is provided. The method includes extracting an incremental voltage to temperature curve for a diode array from a first incremental voltage of the diode array at a first temperature. The diode array and a device under test (DUT) which includes a thermal sensor are heated. After heating the diode array, a first incremental temperature is determined from the incremental voltage to temperature curve for the diode array and a second incremental voltage of the diode array after heating the diode array. An incremental voltage to temperature curve is extracted for the DUT from the first incremental temperature, a first incremental voltage for the DUT at the first temperature, and a second incremental voltage of the DUT after heating the device under test. A temperature error for the thermal sensor is determined from the incremental voltage to temperature curve for the DUT.

Abstract: A thermal sensor in some embodiments comprises two temperature-sensitive branches, each including a thermal-sensing device, such as one or more bipolar-junction transistors, and a current source for generating a current density in the thermal-sensing device to generate a temperature-dependent signal. The thermal sensor further includes a signal processor configured to multiply the temperature-dependent signal from the branches by respective and different gain factors, and combine the resultant signals to generate an output signal that is substantially proportional to the absolute temperature the thermal sensor is disposed at.

Abstract: A middle-range (mid) low dropout (LDO) voltage has both sinking and sourcing current capability. The mid LDO can provide a voltage reference in active mode and power mode for core only design to work in a Safe Operating Area (SOA). The output of mid LDO can track TO power and/or core power dynamically. The mid LDO can comprise a voltage reference generator and a power-down controller connected to an amplifier, which output is connected to a decoupling capacitor. The provision of a high ground signal allows the mid LDO provide the sinking and sourcing currents.

Abstract: Systems and methods are provided for generating a temperature compensated reference voltage. A temperature compensation circuit may include a proportional-to-absolute temperature (PTAT) circuit, and a complementary-to-absolute temperature (CTAT) circuit, with the PTAT circuit and the CTAT circuit including at least one common metal-oxide-semiconductor field-effect transistor (MOSFET) and being configured to collectively generate a reference voltage in response to a regulated current input. The PTAT circuit may be configured to produce an increase in magnitude of the reference voltage with an increase of temperature, and the CTAT circuit may be configured to generated a decrease in magnitude of the reference voltage with the increase of temperature, wherein the increase in magnitude of the reference voltage produced by the PTAT circuit is at least partially offset by the decrease in magnitude of the reference voltage produced by the CTAT circuit.

Abstract: An integrated circuit includes a first metal-insulator-semiconductor capacitor, a second metal-insulator-semiconductor capacitor, and a metal-insulator-metal capacitor. A first terminal of the first metal-insulator-semiconductor capacitor is configured to receive a first reference voltage for a higher voltage domain, while a first terminal of the second metal-insulator-semiconductor capacitor is configured to receive a second reference voltage for the higher voltage domain. A second terminal of the first metal-insulator-semiconductor capacitor is conductively connected to a first terminal of the metal-insulator-metal capacitor, while a second terminal of the second metal-insulator-semiconductor capacitor is conductively connected to a second terminal of the metal-insulator-metal capacitor.

Abstract: A thermal sensor in some embodiments comprises two temperature-sensitive branches, each including a thermal-sensing device, such as one or more bipolar-junction transistors, and a current source for generating a current density in the thermal-sensing device to generate a temperature-dependent signal. The thermal sensor further includes a signal processor configured to multiply the temperature-dependent signal from the branches by respective and different gain factors, and combine the resultant signals to generate an output signal that is substantially proportional to the absolute temperature the thermal sensor is disposed at.

Abstract: A noise detecting circuit including an amplifier circuit, a filtering circuit and a comparing circuit. The amplifier circuit is arranged to amplify an input signal and output an amplified signal, wherein the input signal is received from a circuit to be detected and indicates a noise level of the circuit to be detected. The filtering circuit is coupled to the amplifier circuit and arranged to filter the amplified signal and output a filtered signal. The comparing circuit is coupled to the filtering circuit and arranged to compare the filtered signal to a reference voltage and output an output signal indicating the noise level of the circuit to be detected.

Abstract: A method includes implanting a first dopant having a first dopant type into a substrate to define a plurality of source/drain (S/D) regions. The method further includes implanting a second dopant having the first dopant type into the substrate to define a channel region between adjacent S/D regions of the plurality of S/D regions, wherein a dopant concentration of the second dopant in the channel region is less than half of a dopant concentration of the first dopant in each of the plurality of S/D regions. The method further includes forming a gate stack over the channel region. The method further includes electrically coupling each of the plurality of S/D regions together.

Abstract: Systems and methods are provided for generating a temperature compensated reference voltage. A temperature compensation circuit may include a proportional-to-absolute temperature (PTAT) circuit, and a complementary-to-absolute temperature (CTAT) circuit, with the PTAT circuit and the CTAT circuit including at least one common metal-oxide-semiconductor field-effect transistor (MOSFET) and being configured to collectively generate a reference voltage in response to a regulated current input. The PTAT circuit may be configured to produce an increase in magnitude of the reference voltage with an increase of temperature, and the CTAT circuit may be configured to generated a decrease in magnitude of the reference voltage with the increase of temperature, wherein the increase in magnitude of the reference voltage produced by the PTAT circuit is at least partially offset by the decrease in magnitude of the reference voltage produced by the CTAT circuit.

Abstract: A method of calibrating a thermal sensor device is provided. The method includes extracting an incremental voltage to temperature curve for a diode array from a first incremental voltage of the diode array at a first temperature. The diode array and a device under test (DUT) which includes a thermal sensor are heated. After heating the diode array, a first incremental temperature is determined from the incremental voltage to temperature curve for the diode array and a second incremental voltage of the diode array after heating the diode array. An incremental voltage to temperature curve is extracted for the DUT from the first incremental temperature, a first incremental voltage for the DUT at the first temperature, and a second incremental voltage of the DUT after heating the device under test. A temperature error for the thermal sensor is determined from the incremental voltage to temperature curve for the DUT.

Abstract: Systems and methods are provided for generating a temperature compensated reference voltage. A temperature compensation circuit may include a proportional-to-absolute temperature (PTAT) circuit, and a complementary-to-absolute temperature (CTAT) circuit, with the PTAT circuit and the CTAT circuit including at least one common metal-oxide-semiconductor field-effect transistor (MOSFET) and being configured to collectively generate a reference voltage in response to a regulated current input. The PTAT circuit may be configured to produce an increase in magnitude of the reference voltage with an increase of temperature, and the CTAT circuit may be configured to generated a decrease in magnitude of the reference voltage with the increase of temperature, wherein the increase in magnitude of the reference voltage produced by the PTAT circuit is at least partially offset by the decrease in magnitude of the reference voltage produced by the CTAT circuit.

Abstract: In a compute-in-memory (“CIM”) system, current signals, indicative of the result of a multiply-and-accumulate operation, from a CIM memory circuit are computed by comparing them with reference currents, which are generated by a current digital-to-analog converter (“DAC”) circuit. The memory circuit can include non-volatile memory (“NVM”) elements, which can be multi-level or two-level NVM elements. The characteristic sizes of the memory elements can be binary weighted to correspond to the respective place values in a multi-bit weight and/or a multi-bit input signal. Alternatively, NVM elements of equal size can be used to drive transistors of binary weighted sizes. The current comparison operation can be carried out at higher speeds than voltage computation. In some embodiments, simple clock-gated switches are used to produce even currents in the current summing branches. The clock-gated switches also serve to limit the time the cell currents are on, thereby reducing static power consumption.

Abstract: Circuits and methods for reducing and cancelling out kickback noise are disclosed. In one example, a circuit for a comparator is disclosed. The circuit includes: a first transistor group, a second transistor group, and a first switch. The first transistor group comprises a first transistor having a drain coupled to a first node, and a second transistor having a source coupled to the first node. Gates of the first transistor and the second transistor are coupled together to a first input of the comparator. The second transistor group comprises a third transistor having a drain coupled to a second node, and a fourth transistor having a source coupled to the second node. Gates of the third transistor and the fourth transistor are coupled together to a second input of the comparator. The first switch is connected to and between the first node and the second node.

Abstract: A semiconductor device and a method for a method for manufacturing a semiconductor device are provided. The semiconductor device comprises a core transistor having a drain configured to receive a first voltage, and a first dummy device connected to the drain of the core transistor, the first dummy device having a first dummy transistor and a second dummy transistor. Wherein a gate and a source of the first dummy transistor are connected to each other. Wherein a drain of the second dummy transistor is connected to the source of the first dummy transistor. Wherein a gate of the second dummy transistor is connected to the drain of the core transistor.

Abstract: An integrated circuit includes a first circuit with m first units coupled in parallel, any of the first units including one or more first transistors coupled in series, and a second circuit with n second units coupled in parallel, any of the second units including one or more second transistors coupled in series. A gate terminal of the first circuit is coupled to a gate terminal of the second circuit. M and n are different positive integers.

Abstract: A circuit includes an operational amplifier, a plurality of input capacitors, a plurality of output capacitors, a plurality of sampling switches, a plurality of holding switches, a plurality of combined switches. The input capacitors include a first input capacitor and a second input capacitor. The output capacitors include a first output capacitor and a second output capacitor. The sampling switches include a first sampling switch, a second sampling switch, a third sampling switch and a fourth sampling switch. The holding switches include a first holding switch and a second holding switch. The combined switches include a first combined switch and a second combined switch.

Abstract: A circuit for parameter PSRR measurement includes a filter, a first regulator and a second regulator. The filter may be configured for receiving an AC input signal and a DC input signal, and for outputting a combined output signal according to the AC input signal and the DC input signal. The first regulator may be configured for receiving the combined output signal, and for outputting a first output signal having a first AC component signal and a first DC component signal. The second regulator may be configured for receiving the first output signal, and for outputting a second output signal having a second AC component signal and a second DC component signal. A parameter PSRR of the second regulator may be obtained according to a ratio between the second AC component signal and the first AC component signal.