Patents by Inventor Jaw-Juinn Horng
Jaw-Juinn Horng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230369311Abstract: An integrated circuit includes a first circuit with m first units coupled in parallel, any of the first units including one or more first transistors coupled in series, and a second circuit with n second units coupled in parallel, any of the second units including one or more second transistors coupled in series. A gate terminal of the first circuit is coupled to a gate terminal of the second circuit. M and n are different positive integers.Type: ApplicationFiled: July 30, 2023Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Ho CHANG, Yi-Wen CHEN, Jaw-Juinn HORNG, Yung-Chow PENG
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Publication number: 20230358618Abstract: A device including a first plurality of metal-oxide semiconductor field-effect transistors electrically connected in series. Each of the first plurality of metal-oxide semiconductor field-effect transistors includes a first gate structure, a first drain/source region on one side of the first gate structure, and a second drain/source region on another side of the first gate structure. The first gate structure of each of the first plurality of metal-oxide semiconductor field-effect transistors is configured to receive a bias voltage to bias on the first plurality of metal-oxide semiconductor field-effect transistors and provide a temperature dependent resistance through the first plurality of metal-oxide semiconductor field-effect transistors to measure temperatures.Type: ApplicationFiled: May 3, 2022Publication date: November 9, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jaw-Juinn Horng, Szu-Lin Liu, Yung-Chow Peng, Shenggao LI
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Patent number: 11810813Abstract: A system for designing a temperature sensor arrangement includes a processor and a non-transitory computer readable medium, including instructions, connected to the processor. The processor is configured to execute the instructions for designing a sensor array, the sensor array includes a first transistor of a first device, and a plurality of second transistors of a second device. The processor is configured to execute the instructions for designing a guard ring region between the sensor array and another circuit of an integrated circuit, the guard ring region includes a transistor structure. The processor is configured to execute the instructions for designing a thermally conductive element between the sensor array and the guard ring region, the thermally conductive element is connected to the transistor structure, the first transistor and each of the plurality of second transistors. The processor is configured to execute the instructions for generating the temperature sensor arrangement.Type: GrantFiled: November 17, 2020Date of Patent: November 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jaw-Juinn Horng, Szu-Lin Liu
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Publication number: 20230350442Abstract: Systems and methods as described herein may take a variety of forms. In an example, a circuit includes a first voltage stepdown module and a second voltage stepdown module. The first voltage stepdown module has a supply voltage and a first reference voltage as inputs, and an intermediate stepped down voltage as an output, the intermediate stepped down voltage being electrically coupled to a feedback input of the first voltage stepdown module. The second voltage stepdown module includes a low-dropout voltage regulator having the intermediate stepped down voltage and a second reference voltage as inputs and a target voltage as an output.Type: ApplicationFiled: June 20, 2023Publication date: November 2, 2023Inventors: Bindu Madhavi Kasina, Szu-Chun Tsao, Jaw-Juinn Horng
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Publication number: 20230343785Abstract: A method of manufacturing an integrated circuit (IC) device includes forming a metal oxide semiconductor (MOS) transistor including a first gate and first and second source/drain (S/D) regions, the first and second S/D regions having a first doping type and being formed in a substrate region having a second doping type different from the first doping type, forming a guard ring structure surrounding the MOS transistor, the guard ring structure including a second gate and first and second heavily doped regions, the first and second heavily doped regions being formed in the substrate region and having the second doping type, and constructing a first electrical connection between the first and second gates.Type: ApplicationFiled: June 28, 2023Publication date: October 26, 2023Inventors: Yi-Hsiang WANG, Szu-Lin LIU, Jaw-Juinn HORNG, Yung-Chow PENG
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Patent number: 11791784Abstract: A noise detecting circuit including an amplifier circuit, a filtering circuit and a comparing circuit. The amplifier circuit is arranged to amplify an input signal and output an amplified signal, wherein the input signal is received from a circuit to be detected and indicates a noise level of the circuit to be detected. The filtering circuit is coupled to the amplifier circuit and arranged to filter the amplified signal and output a filtered signal. The comparing circuit is coupled to the filtering circuit and arranged to compare the filtered signal to a reference voltage and output an output signal indicating the noise level of the circuit to be detected.Type: GrantFiled: September 29, 2022Date of Patent: October 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Bei-Shing Lien, Jaw-Juinn Horng
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Patent number: 11791786Abstract: A circuit includes an operational amplifier, a plurality of input capacitors, a plurality of output capacitors, a plurality of sampling switches, a plurality of holding switches, a plurality of combined switches. The input capacitors include a first input capacitor and a second input capacitor. The output capacitors include a first output capacitor and a second output capacitor. The sampling switches include a first sampling switch, a second sampling switch, a third sampling switch and a fourth sampling switch. The holding switches include a first holding switch and a second holding switch. The combined switches include a first combined switch and a second combined switch.Type: GrantFiled: January 11, 2021Date of Patent: October 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Bei-Shing Lien, Jaw-Juinn Horng
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Patent number: 11784617Abstract: Disclosed herein are related to a system and a method of amplifying an input voltage based on cascaded charge pump boosting. In one aspect, first electrical charges are stored at a first capacitor according to the input voltage to obtain a second voltage. In one aspect, the second voltage is amplified according to the first electrical charges stored by the first capacitor to obtain a third voltage. In one aspect, second electrical charges are stored at the second capacitor according to the third voltage. In one aspect, the third voltage is amplified according to the second electrical charges stored by the second capacitor to obtain a fourth voltage.Type: GrantFiled: October 30, 2020Date of Patent: October 10, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chin-Ho Chang, Jaw-Juinn Horng, Yung-Chow Peng
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Publication number: 20230317806Abstract: A method of making a semiconductor device includes forming an active device region in a substrate. The method further includes forming a first transistor in the active device region, the first transistor including a first channel region a first source region and a first drain region. The method further includes forming a guard ring region outside the active device region. The method further includes forming a second transistor in the guard ring region, the second transistor comprising a second channel region a second source region and a second drain region. The second channel region includes a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region.Type: ApplicationFiled: May 24, 2023Publication date: October 5, 2023Inventors: Amit KUNDU, Jaw-Juinn HORNG
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Patent number: 11763891Abstract: Disclosed herein are related to a memory system including a memory cell and a circuit to operate the memory cell. In one aspect, the circuit includes a pair of transistors to electrically couple, to the bit line, a selected one of i) a voltage source to supply a reference voltage to the memory cell and ii a sensor to sense a current through the memory cell. In one aspect, the circuit includes a first transistor. The first transistor and the bit line may be electrically coupled between the pair of transistors and the memory cell in series.Type: GrantFiled: March 9, 2021Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu-Chun Tsao, Jaw-Juinn Horng
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Patent number: 11756950Abstract: An integrated circuit includes a first circuit with m first units coupled in parallel, any of the first units including one or more first transistors coupled in series, and a second circuit with n second units coupled in parallel, any of the second units including one or more second transistors coupled in series. A gate terminal of the first circuit is coupled to a gate terminal of the second circuit. M and n are different positive integers.Type: GrantFiled: June 30, 2021Date of Patent: September 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, LtdInventors: Chin-Ho Chang, Yi-Wen Chen, Jaw-Juinn Horng, Yung-Chow Peng
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Patent number: 11755051Abstract: Systems and methods are provided for generating a temperature compensated reference voltage. A temperature compensation circuit may include a proportional-to-absolute temperature (PTAT) circuit, and a complementary-to-absolute temperature (CTAT) circuit, with the PTAT circuit and the CTAT circuit including at least one common metal-oxide-semiconductor field-effect transistor (MOSFET) and being configured to collectively generate a reference voltage in response to a regulated current input. The PTAT circuit may be configured to produce an increase in magnitude of the reference voltage with an increase of temperature, and the CTAT circuit may be configured to generated a decrease in magnitude of the reference voltage with the increase of temperature, wherein the increase in magnitude of the reference voltage produced by the PTAT circuit is at least partially offset by the decrease in magnitude of the reference voltage produced by the CTAT circuit.Type: GrantFiled: July 26, 2022Date of Patent: September 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Amit Kundu, Jaw-Juinn Horng
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Publication number: 20230268911Abstract: A method includes fabricating a first transistor and a second transistor on a substrate and fabricating a first conducting line and a second conducting line in a first metal layer. The method also includes connecting a gate of the first transistor to the first conducting line and connecting a gate of the second transistor to the second conducting line. The first conducting line and the second conducting line are parallel and adjacent to each other in the first metal layer above the first transistor and the second transistor. The method still includes connecting a source and a drain of the first transistor to a third conducting line.Type: ApplicationFiled: April 25, 2023Publication date: August 24, 2023Inventors: Szu-Lin LIU, Jaw-Juinn HORNG, Yi-Hsiang WANG, Wei-Lin LAI
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Patent number: 11733724Abstract: In some embodiments, an integrated circuit device includes multiple rows of functional cells, with each row having a cell height. At least one of rows of functional cells includes at least one digital low-dropout voltage regulator (DLVR) cell with the cell height for the row. The DLVR cell includes: an input terminal, an output terminal, a voltage supply terminal, a reference voltage terminal, and one or more pairs of transistors. Each pair of transistors are arranged in cascode configuration connected between the voltage supply terminal and output terminal. The gate of one of the transistors the cascode configuration is connected to the input terminal, and the gate of the other transistor in the cascode configuration is connected to the reference voltage terminal. The four terminals each comprises a metal track in the bottom metal layer and disposed within the cell height.Type: GrantFiled: August 20, 2021Date of Patent: August 22, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yu Lai, Szu-Chun Tsao, Jaw-Juinn Horng
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Patent number: 11726510Abstract: Systems and methods as described herein may take a variety of forms. In an example, a circuit includes a first voltage stepdown module and a second voltage stepdown module. The first voltage stepdown module has a supply voltage and a first reference voltage as inputs, and an intermediate stepped down voltage as an output, the intermediate stepped down voltage being electrically coupled to a feedback input of the first voltage stepdown module. The second voltage stepdown module includes a low-dropout voltage regulator having the intermediate stepped down voltage and a second reference voltage as inputs and a target voltage as an output.Type: GrantFiled: August 27, 2021Date of Patent: August 15, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bindu Madhavi Kasina, Szu-Chun Tsao, Jaw-Juinn Horng
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Publication number: 20230244258Abstract: Systems and methods as described herein may take a variety of forms. In one example, systems and methods are provided for a circuit for powering a voltage regulator. A voltage regulator circuit has an output electrically coupled to a gate of an output driver transistor, the output driver transistor having a first terminal electrically coupled to a voltage source and a second terminal electrically coupled to a first terminal of a voltage divider, the voltage divider having an second terminal electrically coupled to ground, and the voltage divider having an output of a stepped down voltage. A power control circuitry transistor has a first terminal electrically coupled to the voltage source, the power control circuitry transistor having a second terminal electrically coupled to the gate terminal of the output driver transistor, and the power control circuitry transistor having a gate terminal electrically coupled to a status voltage signal.Type: ApplicationFiled: April 6, 2023Publication date: August 3, 2023Inventors: Szu-Chun Tsao, Jaw-Juinn Horng, Bindu Madhavi Kasina, Yi-Wen Chen
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Patent number: 11709200Abstract: A method of calibrating a thermal sensor device is provided. The method includes extracting an incremental voltage to temperature curve for a diode array from a first incremental voltage of the diode array at a first temperature. The diode array and a device under test (DUT) which includes a thermal sensor are heated. After heating the diode array, a first incremental temperature is determined from the incremental voltage to temperature curve for the diode array and a second incremental voltage of the diode array after heating the diode array. An incremental voltage to temperature curve is extracted for the DUT from the first incremental temperature, a first incremental voltage for the DUT at the first temperature, and a second incremental voltage of the DUT after heating the device under test. A temperature error for the thermal sensor is determined from the incremental voltage to temperature curve for the DUT.Type: GrantFiled: July 29, 2022Date of Patent: July 25, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu-Lin Liu, Jaw-Juinn Horng
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Publication number: 20230229186Abstract: A bandgap reference (BGR) circuit is provided. The BGR circuit includes a first node, a second node, and a third node. A first resistive element is connected between the second node and the third node. The BGR circuit is operative to provide a reference voltage as an output. The BGR circuit further includes a current shunt path connected between the first node and the third node, the current shunt path being operable to regulate a voltage drop across the first resistive element.Type: ApplicationFiled: March 27, 2023Publication date: July 20, 2023Inventors: JAW-JUINN HORNG, CHIN-HO CHANG, YI-WEN CHEN
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Publication number: 20230231554Abstract: A method (of decoupling from voltage variations in a first voltage drop between first and second reference voltage rails) includes: electrically coupling one or more components to form a decoupling capacitance (decap) circuit; electrically coupling one or more components to form a filtered biasing circuit; and making an unswitched series electrical coupling of the decap circuit and the filtered biasing circuit between the first and second reference voltage rails.Type: ApplicationFiled: March 13, 2023Publication date: July 20, 2023Inventors: Szu-Lin LIU, Yi-Hsiang WANG, Jaw-Juinn HORNG
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Patent number: 11692880Abstract: A three-dimensional integrated circuit includes a first layer including at least one sensing element configured to output at least one temperature-dependent voltage; and a second layer disposed vertically with respect to the first layer and coupled to the first layer by at least one via. The second layer includes: a compare circuit configured to generate at least one intermediate voltage in response to comparing the at least one temperature-dependent voltage to a feedback voltage; a control circuit configured to generate at least one control signal in response to the intermediate voltage; and a switching circuit configured to couple a capacitor coupled to a feedback node to one of a first voltage supply and a second voltage supply in response to the at least one control signal to generate an output signal that is based on a temperature sensed by the sensing element.Type: GrantFiled: January 4, 2021Date of Patent: July 4, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Szu-Lin Liu, Jaw-Juinn Horng, Yung-Chow Peng