Patents by Inventor Jawaharlal Tangudu
Jawaharlal Tangudu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210175914Abstract: Techniques maintaining receiver reliability, including determining a present attenuation level for an attenuator, wherein the attenuation level is set by a gain controller, determining a relative reliability threshold based on the present attenuation level, receiving a radio frequency (RF) signal, determining a voltage level of the received RF signal, comparing the voltage level of the received RF signal to the relative reliability threshold to determine that a reliability condition exists, and overriding, in response to the determination that the reliability condition exists, the present attenuation level set by the gain controller with an override attenuation level based on the present attenuation level.Type: ApplicationFiled: December 4, 2020Publication date: June 10, 2021Inventors: Sarma Sundareswara GUNTURI, Jagannathan VENKATARAMAN, Jawaharlal TANGUDU, Narasimhan RAJAGOPAL, Eeshan MIGLANI
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Publication number: 20210176005Abstract: A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.Type: ApplicationFiled: July 22, 2020Publication date: June 10, 2021Inventors: Sanjay PENNAM, Vamsi Krishna KANDALLA, Brahmendra Reddy YATHAM, Shailesh WARDHEN, Jaiganesh BALAKRISHNAN, Jawaharlal TANGUDU
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Patent number: 11029919Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.Type: GrantFiled: April 20, 2020Date of Patent: June 8, 2021Assignee: Texas Instruments IncorporatedInventors: Jawaharlal Tangudu, Suvam Nandi, Pooja Sundar, Jaiganesh Balakrishnan
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Publication number: 20210159924Abstract: An integrated circuit comprises an input, a digital step attenuator, an analog-to-digital converter, a first output, a second output, a first bandwidth filter, a first band attack detector, a first band decay detector, a second bandwidth filter, a second band attack detector, a second band decay detector, and an automatic gain control. The ADC is configured to output a digital signal including a first and a second frequency range. The first and second bandwidth filters are configured to extract respective digital signals comprising the first and second frequency ranges. The band attack and decay detectors are configured to detect band peaks or decays thereof such that the DSA and External AMP may be controlled by means of the AGC based on the detected band peaks or decays, and ADC attack and ADC decay.Type: ApplicationFiled: November 20, 2020Publication date: May 27, 2021Inventors: Jawaharlal Tangudu, Yeswanth Guntupalli, Kalyan Gudipati, Robert Clair Keller, Wenjing Lu, Jaiganesh Balakrishnan, Harsh Garg, Bragadeesh S, Raju Kharataram Chaudhari, Francesco Dantoni
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Patent number: 10979262Abstract: IQ mismatch correction for analog chain IQ mismatch impairments is based on a two-filter architecture. In either RX or TX, an IQmc mismatch corrector (digital chain) filters I and Q digital signals, and includes an I-path to receive the I signal, and a Q-path to receive the Q signal, and is configured with two filters: an in-path filter to filter either the I signal or the Q signal received in the same path; and a cross-path filter to filter either the I signal or the Q signal received in the other path. The IQmc mismatch corrector can include: an I-path delay element to provide a delay to the I signal corresponding to a delay through either the in-path filter or the cross-path filter; and a Q-path delay element to provide a delay to the Q signal corresponding to a delay through either the in-path filter or the cross-path filter.Type: GrantFiled: June 16, 2020Date of Patent: April 13, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jawaharlal Tangudu, Sthanunathan Ramakrishnan, Jaiganesh Balakrishnan
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Publication number: 20210105019Abstract: A method for non-linearity correction includes receiving a first output signal from a data signal path containing a first analog-to-digital converter and receiving a second output signal from a second analog-to-digital converter. The method also includes generating first non-linearity coefficients using the first output signal and generating second non-linearity coefficients using the first and second output signals. The method further includes applying, by a non-linearity corrector in the data signal path, the first and second non-linearity coefficients to compensate for non-linearity components in a digitized signal output from the first analog-to-digital converter to generate a corrected digitized signal.Type: ApplicationFiled: October 5, 2020Publication date: April 8, 2021Inventors: Pankaj Gupta, Jawaharlal Tangudu, Ajai Paulose
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Publication number: 20210105021Abstract: A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit.Type: ApplicationFiled: October 2, 2020Publication date: April 8, 2021Inventors: Jawaharlal TANGUDU, Pankaj GUPTA, Sreenath Narayanan POTTY, Ajai PAULOSE, Chandrasekhar SRIRAM, Mahesh Ravi VARMA, Shabbar Abbasi VEJLANI, Neeraj SHRIVASTAVA, Himanshu VARSHNEY, Divyeshkumar Mahendrabhai PATEL, Raju Kharataram CHAUDHARI
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Publication number: 20210083697Abstract: An IQ mismatch estimation circuit includes a raw channel estimation circuit, a reference channel estimation circuit, a digital predistortion (DPD) bin identification circuit, a channel estimate pruning circuit, and an IQ correction coefficient generation circuit. The raw channel estimation circuit generates raw channel estimates for a plurality of frequency bins of a baseband signal. The reference channel estimation circuit identifies a reference channel estimate based on the raw channel estimates. The DPD bin identification circuit identifies, based on the reference channel estimate, the frequency bins for which the raw channel estimates are based on a DPD expansion signal. The channel estimate pruning circuit generates pruned raw channel estimates by discarding the raw channel estimates of the frequency bins identified by the DPD bin identification circuit. The IQ correction coefficient generation circuit generates IQ mismatch correction coefficients based on the pruned raw channel estimates.Type: ApplicationFiled: July 30, 2020Publication date: March 18, 2021Inventors: Sashidharan Venkatraman, Jawaharlal Tangudu, Sarma Sundareswara Gunturi, Ram Narayan Krishna Nama Mony
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Publication number: 20210075368Abstract: A phase coherent NCO circuit includes a base frequency NCO, a phase seeding circuit, a scaled frequency NCO, a sine/cosine generator. The base frequency NCO is configured to generate base phase values based on a base frequency control word. The phase seeding circuit is coupled to the base frequency NCO. The phase seeding circuit is configured to generate a seed phase value based on the base phase values and a scale factor value. The scaled frequency NCO is coupled to the phase seeding circuit. The scaled frequency NCO is configured to generate oscillator phase values based on the phase seed value and an oscillator frequency control word. The sine/cosine generator is coupled to the scaled frequency NCO. The sine/cosine generator is configured to generate oscillator output samples based on the oscillator phase values.Type: ApplicationFiled: November 20, 2020Publication date: March 11, 2021Inventors: Nagalinga Swamy Basayya AREMALLAPUR, Sriram MURALI, Jawaharlal TANGUDU
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Patent number: 10911057Abstract: A digital clock generator for a digital clock domain interfaced to another clock domain through a FIFO, includes division selector circuitry to provide an input randomizing sequence of clock division factors, selected from a defined set of clock division factors corresponding to a target average clock division, and division arbitration circuitry to generate a drift-corrected randomizing sequence of clock division factors, based at least in part on the input randomizing sequence of clock division factors, and an accumulated drift correction signal. A clock drift control loop generates the accumulated drift correction signal, based at least in part on an accumulated clock drift relative to the target average clock division. Clock generation can be based on randomized division with the drift-corrected randomizing sequence of clock division factors. The drift-corrected randomizing sequence of clock division factors can be generated so that clock drift is bounded based on a FIFO depth.Type: GrantFiled: November 11, 2019Date of Patent: February 2, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sarma Sundareswara Gunturi, Jawaharlal Tangudu, Sundarrajan Rangachari
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Patent number: 10879845Abstract: A phase coherent NCO circuit includes a base frequency NCO, a phase seeding circuit, a scaled frequency NCO, a sine/cosine generator. The base frequency NCO is configured to generate base phase values based on a base frequency control word. The phase seeding circuit is coupled to the base frequency NCO. The phase seeding circuit is configured to generate a seed phase value based on the base phase values and a scale factor value. The scaled frequency NCO is coupled to the phase seeding circuit. The scaled frequency NCO is configured to generate oscillator phase values based on the phase seed value and an oscillator frequency control word. The sine/cosine generator is coupled to the scaled frequency NCO. The sine/cosine generator is configured to generate oscillator output samples based on the oscillator phase values.Type: GrantFiled: May 6, 2019Date of Patent: December 29, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Nagalinga Swamy Basayya Aremallapur, Sriram Murali, Jawaharlal Tangudu
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Patent number: 10812294Abstract: A channel estimation method and system for IQ imbalance and local oscillator leakage correction, wherein an example of a channel estimation system comprising a calibrating signal generator configured to generate at least one pair of calibrating signals, a feedback IQ mismatch estimator configured to measure feedback IQ mismatch estimates based on the pair of calibrating signals, and a calibrating signal based channel estimator configured to generate a channel estimate based on the pair of calibrating signals and the feedback IQ mismatch estimates.Type: GrantFiled: November 15, 2019Date of Patent: October 20, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jawaharlal Tangudu, Sashidharan Venkatraman, Sarma Sundareswara Gunturi, Chandrasekhar Sriram, Sthanunathan Ramakrishnan, Ram Narayan Krishna Nama Mony
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Publication number: 20200322067Abstract: A channel response generating module and method for generating a channel response based on a ratio of a channel response corresponding to an image signal frequency bin in relation to a channel response corresponding to a traffic signal frequency bin, or a channel response corresponding to a first frequency bin in relation to a channel response corresponding to a second frequency bin, and a zero-IF signal transmitter employing the channel response generating module and method to efficiently suppress image signals or compensate traffic signals during transmission of IQ RF signals.Type: ApplicationFiled: June 19, 2020Publication date: October 8, 2020Inventors: Sarma Sundareswara GUNTURI, Chandrasekhar SRIRAM, Jawaharlal TANGUDU, Sashidharan VENKATRAMAN
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Publication number: 20200313944Abstract: IQ mismatch correction for analog chain IQ mismatch impairments is based on a two-filter architecture. In either RX or TX, an IQmc mismatch corrector (digital chain) filters I and Q digital signals, and includes an I-path to receive the I signal, and a Q-path to receive the Q signal, and is configured with two filters: an in-path filter to filter either the I signal or the Q signal received in the same path; and a cross-path filter to filter either the I signal or the Q signal received in the other path. The IQmc mismatch corrector can include: an I-path delay element to provide a delay to the I signal corresponding to a delay through either the in-path filter or the cross-path filter; and a Q-path delay element to provide a delay to the Q signal corresponding to a delay through either the in-path filter or the cross-path filter.Type: ApplicationFiled: June 16, 2020Publication date: October 1, 2020Inventors: Jawaharlal Tangudu, Sthanunathan Ramakrishnan, Jaiganesh Balakrishnan
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Publication number: 20200301666Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.Type: ApplicationFiled: April 20, 2020Publication date: September 24, 2020Inventors: Jawaharlal Tangudu, Suvam Nandi, Pooja Sundar, Jaiganesh Balakrishnan
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Patent number: 10778344Abstract: A channel response generating module and method for generating a channel response based on a ratio of a channel response corresponding to an image signal frequency bin in relation to a channel response corresponding to a traffic signal frequency bin, or a channel response corresponding to a first frequency bin in relation to a channel response corresponding to a second frequency bin, and a zero-IF signal transmitter employing the channel response generating module and method to efficiently suppress image signals or compensate traffic signals during transmission of IQ RF signals.Type: GrantFiled: October 23, 2019Date of Patent: September 15, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sarma Sundareswara Gunturi, Chandrasekhar Sriram, Jawaharlal Tangudu, Sashidharan Venkatraman
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Patent number: 10715376Abstract: An IQ mismatch correction function generator configured to generate an enhanced IQ mismatch correction function to improve the compensation for IQ mismatch, and an IQ signal receiver with the IQ mismatch correction function generator, wherein the enhanced IQ mismatch correction function is determined based on an initial IQ mismatch correction function derived from IQ mismatch estimates corresponding to frequency bins where signals are present and error of the initial IQ mismatch correction function by comparing the values of the initial IQ mismatch correction function with IQ mismatch estimates corresponding to a respective bin of the frequency bins.Type: GrantFiled: June 18, 2019Date of Patent: July 14, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jaiganesh Balakrishnan, Jawaharlal Tangudu, Sthanunathan Ramakrishnan, Chandrasekhar Sriram
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Publication number: 20200212844Abstract: A phase coherent NCO circuit includes a base frequency NCO, a phase seeding circuit, a scaled frequency NCO, a sine/cosine generator. The base frequency NCO is configured to generate base phase values based on a base frequency control word. The phase seeding circuit is coupled to the base frequency NCO. The phase seeding circuit is configured to generate a seed phase value based on the base phase values and a scale factor value. The scaled frequency NCO is coupled to the phase seeding circuit. The scaled frequency NCO is configured to generate oscillator phase values based on the phase seed value and an oscillator frequency control word. The sine/cosine generator is coupled to the scaled frequency NCO. The sine/cosine generator is configured to generate oscillator output samples based on the oscillator phase values.Type: ApplicationFiled: May 6, 2019Publication date: July 2, 2020Inventors: Nagalinga Swamy Basayya AREMALLAPUR, Sriram MURALI, Jawaharlal TANGUDU
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Publication number: 20200177417Abstract: An electrical system includes a transceiver with an IQ estimator and an IQ mismatch corrector. The electrical system also includes an antenna coupled to the transceiver. The IQ estimator is configured to perform frequency-domain IQ mismatch analysis to determine an IQ mismatch estimate at available frequency bins of a baseband data signal. The IQ mismatch corrector is configured to correct the baseband data signal based on the IQ mismatch estimate.Type: ApplicationFiled: November 26, 2019Publication date: June 4, 2020Inventors: Jawaharlal TANGUDU, Sashidharan VENKATRAMAN, Sundarrajan RANGACHARI, Sarma Sundareswara GUNTURI, Sthanunathan RAMAKRISHNAN
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Publication number: 20200169434Abstract: A channel estimation method and system for IQ imbalance and local oscillator leakage correction, wherein an example of a channel estimation system comprising a calibrating signal generator configured to generate at least one pair of calibrating signals, a feedback IQ mismatch estimator configured to measure feedback IQ mismatch estimates based on the pair of calibrating signals, and a calibrating signal based channel estimator configured to generate a channel estimate based on the pair of calibrating signals and the feedback IQ mismatch estimates.Type: ApplicationFiled: November 15, 2019Publication date: May 28, 2020Inventors: Jawaharlal TANGUDU, Sashidharan VENKATRAMAN, Sarma Sundareswara GUNTURI, Chandrasekhar SRIRAM, Sthanunathan RAMAKRISHNAN, Ram Narayan KRISHNA NAMA MONY