Abstract: A phase spectrum based delay estimating method of tracking channel responses, extracting phase responses from the tracked channel responses, and generating a delay estimate, wherein the delay estimate is based on a slope and intercept estimates of the extracted phase responses with high quality metric to improve delay estimation, and a system thereof.

Abstract: A non-linearity correction module, an optional droop corrector, and a zero-IF receiver with the non-linearity correction module and an optional droop corrector, wherein the non-linearity correction module is configured to generate a non-linearity term scaled to mitigate an inter-modulation component term of a RF signal received by the zero-IF receiver based on a test signal to enhance linearity in the zero-IF receiver and the optional droop corrector is configured to compensate a droop within a signal band of interest, caused by an analog low pass filter filtering a RF signal received by the zero-IF receiver, before a down-converted RF signal is fed into the non-linearity module.

Abstract: A digital down converter includes a low resolution mixer, a decimation filter, and a high resolution mixer. The low resolution mixer is configured to receive a digitized radio frequency signal, and apply a first down conversion to the radio frequency signal to produce an intermediate frequency signal. The decimation filter is coupled to the low resolution mixer. The decimation filter is configured to receive the intermediate frequency signal, and reduce a sampling rate of the intermediate frequency signal to produce a decimated intermediate frequency signal. The high resolution mixer is coupled to the decimation filter. The high resolution mixer is configured to receive the decimated intermediate frequency signal, and apply a second down conversion to the decimated intermediate frequency signal to produce a down converted signal.

Abstract: A digital clock generator for a digital clock domain interfaced to another clock domain through a FIFO, includes division selector circuitry to provide an input randomizing sequence of clock division factors, selected from a defined set of clock division factors corresponding to a target average clock division, and division arbitration circuitry to generate a drift-corrected randomizing sequence of clock division factors, based at least in part on the input randomizing sequence of clock division factors, and an accumulated drift correction signal. A clock drift control loop generates the accumulated drift correction signal, based at least in part on an accumulated clock drift relative to the target average clock division. Clock generation can be based on randomized division with the drift-corrected randomizing sequence of clock division factors. The drift-corrected randomizing sequence of clock division factors can be generated so that clock drift is bounded based on a FIFO depth.

Abstract: A channel response generating module and method for generating a channel response based on a ratio of a channel response corresponding to an image signal frequency bin in relation to a channel response corresponding to a traffic signal frequency bin, or a channel response corresponding to a first frequency bin in relation to a channel response corresponding to a second frequency bin, and a zero-IF signal transmitter employing the channel response generating module and method to efficiently suppress image signals or compensate traffic signals during transmission of IQ RF signals.

Abstract: An IQ mismatch correction function generator configured to generate an enhanced IQ mismatch correction function to improve the compensation for IQ mismatch, and an IQ signal receiver with the IQ mismatch correction function generator, wherein the enhanced IQ mismatch correction function is determined based on an initial IQ mismatch correction function derived from IQ mismatch estimates corresponding to frequency bins where signals are present and error of the initial IQ mismatch correction function by comparing the values of the initial IQ mismatch correction function with IQ mismatch estimates corresponding to a respective bin of the frequency bins.

Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.

Abstract: A circuit for digital filtering an analog signal converted to digital, including an analog circuit to generate an analog signal, the analog signal including phase and/or gain errors. An analog-to-digital converter (ADC) to convert the analog signal to a digital signal output to a digital signal path. A frequency-dependent corrector filter included in the digital signal path, and configured as a parameterized filter, the parameterized filter configurable based on the DSA control signal with at least one complex filter parameter for each DSA attenuation step, to correct frequency-dependent errors in phase and/or gain.

Abstract: A re-sampler comprises a first CSD multiplier configured to receive input samples, a first accumulator coupled to the first CSD multiplier and configured to form a first MAC unit with the first CSD multiplier, a second CSD multiplier configured to receive the input samples, and a second accumulator coupled to the second CSD multiplier and configured to form a second MAC unit with the second CSD multiplier, wherein the re-sampler is configured to generate output samples based on the input samples. A method comprises receiving, by a first CSD multiplier, input samples, receiving, by a second CSD multiplier, the input samples, generating coefficients, scaling, using the first CSD multiplier and the second CSD multiplier, the input samples with coefficient vectors associated with the coefficients to form coefficient vector scaled input samples, and generating output samples based on the coefficient vector scaled input samples. The CSD multipliers may be MC-CSD multipliers.

Abstract: IQ mismatch correction for analog chain IQ mismatch impairments is based on a two-filter architecture. In either RX or TX, an IQmc mismatch corrector (digital chain) filters I and Q digital signals, and includes an I-path to receive the I signal, and a Q-path to receive the Q signal, and is configured with two filters: an in-path filter to filter either the I signal or the Q signal received in the same path; and a cross-path filter to filter either the I signal or the Q signal received in the other path. The IQmc mismatch corrector can include: an I-path delay element to provide a delay to the I signal corresponding to a delay through either the in-path filter or the cross-path filter; and a Q-path delay element to provide a delay to the Q signal corresponding to a delay through either the in-path filter or the cross-path filter.

Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.

Abstract: A GNSS receiver to track low power GNSS satellite signals. The GNSS receiver includes a frequency locked loop (FLL) that measures a current doppler frequency of the satellite signal. A delay locked loop (DLL) measures a current code phase delay of the satellite signal. A current operating point corresponds to the current doppler frequency and the current code phase delay of the satellite signal. A grid monitor receives the satellite signal and the current operating point, and measures a satellite signal strength at a plurality of predefined offset points from the current operating point. The FLL and the DLL are centered at the current operating point. A peak detector is coupled to the grid monitor and processes the satellite signal strengths at the plurality of predefined offset points and re-centers the FLL and the DLL to a predefined offset point with the satellite signal strength above a predefined threshold.

Abstract: A zero-insertion FIR filter architecture for filtering a signal with a target band and a secondary band. Digital filter circuitry includes an L-tap FIR (finite impulse response) filter, with a number L filter tap elements (L=0, 1, 2, . . . (L?1)), each with an assigned coefficient from a defined coefficient sequence. The L-tap FIR filter is configurable with a defined zero-insertion coefficient sequence of a repeating sub-sequence of a nonzero coefficient followed by one or more zero-inserted coefficients, with a number Nj of nonzero coefficients, and a number Nk of zero-inserted coefficients, so that L=Nj+Nk. The L-tap FIR filter is configurable as an M-tap FIR filter with a nonzero coefficient sequence in which each of the L filter tap elements is assigned a non-zero coefficient, the M-tap FIR filter having an effective length of M=(Nj+Nk) non-zero coefficients.

Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.

Abstract: In some embodiments, a multiplier-based programmable filter comprises a pre-scaling circuit, a first multiplier circuit coupled to a first output of the pre-scaling circuit and a second output of the pre-scaling circuit, and a second multiplier circuit coupled to the first output of the pre-scaling circuit and the second output of the pre-scaling circuit. In some embodiments, the multiplier-based programmable filter also comprises a first adder coupled to a first output of the first multiplier circuit and a second output of the first multiplier circuit, a second adder coupled to a first output of the second multiplier circuit and a second output of the second multiplier circuit, first register coupled to an output of the first adder and an input of the second adder, and a second register coupled to an output of the second adder.

Abstract: In some embodiments, a multiplier-based programmable filter comprises a pre-scaling circuit, a first multiplier circuit coupled to a first output of the pre-scaling circuit and a second output of the pre-scaling circuit, and a second multiplier circuit coupled to the first output of the pre-scaling circuit and the second output of the pre-scaling circuit. In some embodiments, the multiplier-based programmable filter also comprises a first adder coupled to a first output of the first multiplier circuit and a second output of the first multiplier circuit, a second adder coupled to a first output of the second multiplier circuit and a second output of the second multiplier circuit, first register coupled to an output of the first adder and an input of the second adder, and a second register coupled to an output of the second adder.

Abstract: An integrated circuit chip includes an interleaved analog-to-digital converter (ADC) and an interleaving calibration circuit. The interleaved ADC includes a plurality of ADCs that are each configured to sample an analog signal. The interleaved ADC is configured to convert the analog signal into an interleaved analog-to-digital signal (IADC signal) that includes a plurality of spurious signals formed from mismatches between the plurality of ADCs. The interleaving calibration circuit is configured to receive the IADC signal from the interleaved ADC, generate a mismatch profile estimate corresponding to the plurality of spurious signals to generate one or more mismatch profile estimates, determine whether a first mismatch profile estimate is in a frequency band of interest, and, in response to a determination that the first mismatch profile estimate is in the frequency band of interest, generate a set of model parameters based on the first mismatch profile estimate.

Abstract: A receiver (100) is provided for signals of different signal strengths and modulated with respective pseudorandom noise (PN) codes. The receiver (100) includes a correlator circuit (120) operable to correlate the signals with a selectable locally-issued PN code having a Doppler and a code lag to produce a peak, the correlator circuit (120) being subject to cross correlation with a distinct PN code carried by least one of the signals that can produce cross correlation; and a cross correlation circuit (370, 400) operable to generate a variable comparison value related to the cross correlation as a function of values representing a Doppler difference and a code lag difference between the locally-issued PN code and the distinct PN code, and to use the variable comparison value to reject the peak as invalid from cross correlation or to pass the peak as a valid received peak.

Abstract: A circuit for digital filtering an analog signal converted to digital, including an analog circuit to generate an analog signal, the analog signal including phase and/or gain errors. An analog-to-digital converter (ADC) to convert the analog signal to a digital signal output to a digital signal path. A frequency-dependent corrector filter included in the digital signal path, and configured as a parameterized filter, the parameterized filter configurable based on the DSA control signal with at least one complex filter parameter for each DSA attenuation step, to correct frequency-dependent errors in phase and/or gain.

Abstract: The disclosure provides a radar apparatus for estimating a range of an obstacle. The radar apparatus includes a local oscillator that generates a first ramp segment and a second ramp segment. The first ramp segment and the second ramp segment each includes a start frequency, a first frequency and a second frequency. The first frequency of the second ramp segment is equal to or greater than the second frequency of the first ramp segment when a slope of the first ramp segment and a slope of the second ramp segment are equal and positive. The first frequency of the second ramp segment is equal to or less than the second frequency of the first ramp segment when the slope of the first ramp segment and the slope of the second ramp segment are equal and negative.