Abstract: The disclosure provides a radar apparatus for estimating a range of an obstacle. The radar apparatus includes a local oscillator that generates a first ramp segment and a second ramp segment. The first ramp segment and the second ramp segment each includes a start frequency, a first frequency and a second frequency. The first frequency of the second ramp segment is equal to or greater than the second frequency of the first ramp segment when a slope of the first ramp segment and a slope of the second ramp segment are equal and positive. The first frequency of the second ramp segment is equal to or less than the second frequency of the first ramp segment when the slope of the first ramp segment and the slope of the second ramp segment are equal and negative.

Abstract: The disclosure provides a radar apparatus for estimating a range of an obstacle. The radar apparatus includes a local oscillator that generates a first ramp segment and a second ramp segment. The first ramp segment and the second ramp segment each includes a start frequency, a first frequency and a second frequency. The first frequency of the second ramp segment is equal to or greater than the second frequency of the first ramp segment when a slope of the first ramp segment and a slope of the second ramp segment are equal and positive. The first frequency of the second ramp segment is equal to or less than the second frequency of the first ramp segment when the slope of the first ramp segment and the slope of the second ramp segment are equal and negative.

Abstract: A digital down converter includes a low resolution mixer, a decimation filter, and a high resolution mixer. The low resolution mixer is configured to receive a digitized radio frequency signal, and apply a first down conversion to the radio frequency signal to produce an intermediate frequency signal. The decimation filter is coupled to the low resolution mixer. The decimation filter is configured to receive the intermediate frequency signal, and reduce a sampling rate of the intermediate frequency signal to produce a decimated intermediate frequency signal. The high resolution mixer is coupled to the decimation filter. The high resolution mixer is configured to receive the decimated intermediate frequency signal, and apply a second down conversion to the decimated intermediate frequency signal to produce a down converted signal.

Abstract: Methods and apparatus for reducing non-linearity in analog to digital converters are disclosed. An example apparatus includes an analog-to-digital converter to convert an analog signal into a digital signal; and a non-linearity corrector coupled to the analog-to-digital converter to determine a derivative of the digital signal; determine cross terms including a combination of the digital signal and the derivative of the digital signal; and determine a non-linearity term corresponding to a combination of the cross terms.

Abstract: An integrated circuit chip includes an interleaved analog-to-digital converter (ADC) and an interleaving calibration circuit. The interleaved ADC includes a plurality of ADCs that are each configured to sample an analog signal. The interleaved ADC is configured to convert the analog signal into an interleaved analog-to-digital signal (IADC signal) that includes a plurality of spurious signals formed from mismatches between the plurality of ADCs. The interleaving calibration circuit is configured to receive the IADC signal from the interleaved ADC, generate a mismatch profile estimate corresponding to the plurality of spurious signals to generate one or more mismatch profile estimates, determine whether a first mismatch profile estimate is in a frequency band of interest, and, in response to a determination that the first mismatch profile estimate is in the frequency band of interest, generate a set of model parameters based on the first mismatch profile estimate.

Abstract: A digital down converter includes a low resolution mixer, a decimation filter, and a high resolution mixer. The low resolution mixer is configured to receive a digitized radio frequency signal, and apply a first down conversion to the radio frequency signal to produce an intermediate frequency signal. The decimation filter is coupled to the low resolution mixer. The decimation filter is configured to receive the intermediate frequency signal, and reduce a sampling rate of the intermediate frequency signal to produce a decimated intermediate frequency signal. The high resolution mixer is coupled to the decimation filter. The high resolution mixer is configured to receive the decimated intermediate frequency signal, and apply a second down conversion to the decimated intermediate frequency signal to produce a down converted signal.

Abstract: Circuitry for correcting non-linearity of an analog-to-digital converter. A non-linearity correction system for an analog-to-digital converter (ADC) includes coefficient storage, coefficient transformation circuitry, and correction circuitry. The coefficient storage is encoded with a first set of coefficients for correcting non-linearity of the ADC at a first sampling rate. The coefficient transformation circuitry is coupled to the coefficient storage. The coefficient transformation circuitry is configured to generate a second set of coefficients for correcting non-linearity of the ADC at a different sampling rate. The correction circuitry is configured to apply the second set of coefficients to correct non-linearity in output of the ADC while the ADC is operating at the different sampling rate.

Abstract: Circuitry for correcting non-linearity of an analog-to-digital converter. A non-linearity correction system for an analog-to-digital converter (ADC) includes coefficient storage, coefficient transformation circuitry, and correction circuitry. The coefficient storage is encoded with a first set of coefficients for correcting non-linearity of the ADC at a first sampling rate. The coefficient transformation circuitry is coupled to the coefficient storage. The coefficient transformation circuitry is configured to generate a second set of coefficients for correcting non-linearity of the ADC at a different sampling rate. The correction circuitry is configured to apply the second set of coefficients to correct non-linearity in output of the ADC while the ADC is operating at the different sampling rate.

Abstract: A re-sampler comprises: a plurality of multipliers configured to receive an input sample; and a plurality of accumulators coupled to the multipliers and configured to form multiplier-accumulator (MAC) units with the multipliers, wherein the MAC units are configured to: compute partial products from the input sample, accumulate the partial products over clock cycles, and sequentially generate output samples based on the computing and the accumulating. A method comprises: receiving input samples; computing partial products from the input samples; accumulating the partial products over clock cycles; and sequentially generating output samples based on the computing and the accumulating.

Abstract: Enhancing search capacity of Global Navigation Satellite System (GNSS) receivers. A method for searching satellite signals in a receiver includes performing a plurality of searches sequentially. The method also includes storing a result from each search of the plurality of searches in a consecutive section of a memory. Further, the method includes detecting free sections in the memory. The method also includes concatenating the free sections in the memory to yield a concatenated free section. Moreover, the method includes allocating the concatenated free section for performing an additional search.

Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.

Abstract: A digital down converter includes a low resolution mixer, a decimation filter, and a high resolution mixer. The low resolution mixer is configured to receive a digitized radio frequency signal, and apply a first down conversion to the radio frequency signal to produce an intermediate frequency signal. The decimation filter is coupled to the low resolution mixer. The decimation filter is configured to receive the intermediate frequency signal, and reduce a sampling rate of the intermediate frequency signal to produce a decimated intermediate frequency signal. The high resolution mixer is coupled to the decimation filter. The high resolution mixer is configured to receive the decimated intermediate frequency signal, and apply a second down conversion to the decimated intermediate frequency signal to produce a down converted signal.

Abstract: Methods and apparatus for reducing non-linearity in analog to digital converters are disclosed. An example apparatus includes an analog-to-digital converter to convert an analog signal into a digital signal; and a non-linearity corrector coupled to the analog-to-digital converter to determine a derivative of the digital signal; determine cross terms including a combination of the digital signal and the derivative of the digital signal; and determine a non-linearity term corresponding to a combination of the cross terms.

Abstract: A device includes a circuit board having thereon, a controlling component, a first radar chip and a second radar chip. The first radar chip includes a first radar transmission antenna, a second radar transmission antenna and a first radar receiver antenna array. The second radar chip includes a second radar receiver antenna array. The controlling component can control the first radar chip and the second radar chip. The first radar transmission antenna can transmit a first radar transmission signal. The second radar transmission antenna can transmit a second radar transmission signal. The second radar chip is spaced from the first radar chip so as to create a virtual receiver antenna array between the first radar receiver antenna array and the second radar receiver antenna array.

Abstract: A GNSS receiver configured to detect a presence of at least one GNSS satellite signal in a received signal is provided. The GNSS receiver includes a buffer loaded with sample sets corresponding to the received signal and a Doppler derotation block configured to perform a Doppler derotation corresponding to at least one Doppler frequency on a sample set received from the buffer. The GNSS receiver further includes an accumulator block configured to perform a coherent accumulation of a plurality of sample sets upon or subsequent to the Doppler derotation corresponding to a Doppler frequency, and, a first memory configured to store the results of the coherent accumulation. A register array is configured to be loaded with the results stored in the first memory and a correlator engine is configured to generate correlation results by correlating the results in the register array with a plurality of code phases of GNSS satellites.

Abstract: A method of acquiring a satellite signal in a GNSS receiver includes multiplying a received signal with a hypothesized doppler frequency signal to generate a frequency shifted signal. A PN code sequence signal is multiplied with the frequency shifted signal to generate a PN wiped signal. A windowing function signal is multiplied with the PN wiped signal to generate a windowed signal. The windowed signal is integrated coherently for a first predefined time to generate a coherent accumulated data.

Abstract: A re-sampler comprises a first CSD multiplier configured to receive input samples, a first accumulator coupled to the first CSD multiplier and configured to form a first MAC unit with the first CSD multiplier, a second CSD multiplier configured to receive the input samples, and a second accumulator coupled to the second CSD multiplier and configured to form a second MAC unit with the second CSD multiplier, wherein the re-sampler is configured to generate output samples based on the input samples. A method comprises receiving, by a first CSD multiplier, input samples, receiving, by a second CSD multiplier, the input samples, generating coefficients, scaling, using the first CSD multiplier and the second CSD multiplier, the input samples with coefficient vectors associated with the coefficients to form coefficient vector scaled input samples, and generating output samples based on the coefficient vector scaled input samples. The CSD multipliers may be MC-CSD multipliers.

Abstract: A re-sampler comprises: a plurality of multipliers configured to receive an input sample; and a plurality of accumulators coupled to the multipliers and configured to form multiplier-accumulator (MAC) units with the multipliers, wherein the MAC units are configured to: compute partial products from the input sample, accumulate the partial products over clock cycles, and sequentially generate output samples based on the computing and the accumulating. A method comprises: receiving input samples; computing partial products from the input samples; accumulating the partial products over clock cycles; and sequentially generating output samples based on the computing and the accumulating.

Abstract: Example embodiments of the systems and methods of variable fractional rate digital resampling as disclosed herein achieve variable rate conversion. In the example embodiments, the input samples are upsampled by a factor N in an upsampler followed by a filter which then goes through a linear interpolator. The filter cleans the spectral images of the signal created due to the upsampling operation.

Abstract: A receiver (100) is provided for signals of different signal strengths and modulated with respective pseudorandom noise (PN) codes. The receiver (100) includes a correlator circuit (120) operable to correlate the signals with a selectable locally-issued PN code having a Doppler and a code lag to produce a peak, the correlator circuit (120) being subject to cross correlation with a distinct PN code carried by least one of the signals that can produce cross correlation; and a cross correlation circuit (370, 400) operable to generate a variable comparison value related to the cross correlation as a function of values representing a Doppler difference and a code lag difference between the locally-issued PN code and the distinct PN code, and to use the variable comparison value to reject the peak as invalid from cross correlation or to pass the peak as a valid received peak.