Patents by Inventor Jean Fompeyrine
Jean Fompeyrine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9735010Abstract: A semiconductor substrate is a provided and an insulating layer is formed thereon. A cavity structure is formed above the insulating layer, including a lateral growth channel and a fin seed structure arranged in the lateral growth channel. The fin seed structure provides a seed surface for growing a fin structure. One or more first semiconductor structures of a first semiconductor material and one or more second semiconductor structures of a second, different, semiconductor material are grown sequentially in the growth channel from the seed surface in an alternating way. The first semiconductor structures provide a seed surface for the second semiconductor structures and the second semiconductor structures provide a seed surface for the first semiconductor structures. The second semiconductor structures are selectively etched, thereby forming the fin structure comprising a plurality of parallel fins of the first semiconductor structures. Corresponding semiconductor structures are also included.Type: GrantFiled: May 27, 2016Date of Patent: August 15, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniele Caimi, Lukas Czornomaz, Jean Fompeyrine, Emanuele Uccelli
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Publication number: 20170229460Abstract: A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including SixGe1?x where x=0 to 1 and the second semiconductor material including a group III-V compound material. A first gate stack on the first channel structure includes: a first native oxide layer as an interface control layer, the first native oxide layer comprising an oxide of the first semiconductor material; a first high-k dielectric layer; a first metal gate layer. A second gate stack on the second channel structure includes a second high-k dielectric layer; a second metal gate layer. The interface between the second channel structure and the second high-k dielectric layer is free of any native oxides of the second semiconductor material.Type: ApplicationFiled: February 10, 2016Publication date: August 10, 2017Inventors: Lukas CZORNOMAZ, Veeresh Vidyadhar DESHPANDE, Vladimir DJARA, Jean FOMPEYRINE
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Publication number: 20170229352Abstract: A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including SixGe1-x where x=0 to 1 and the second semiconductor material including a group III-V compound material. A first gate stack on the first channel structure includes: a first native oxide layer as an interface control layer, the first native oxide layer comprising an oxide of the first semiconductor material; a first high-k dielectric layer; a first metal gate layer. A second gate stack on the second channel structure includes a second high-k dielectric layer; a second metal gate layer. The interface between the second channel structure and the second high-k dielectric layer is free of any native oxides of the second semiconductor material.Type: ApplicationFiled: April 10, 2017Publication date: August 10, 2017Inventors: Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vladimir Djara, Jean Fompeyrine
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Patent number: 9704757Abstract: The invention relates to a method for fabricating a semiconductor circuit comprising providing a semiconductor substrate; fabricating a first semiconductor device comprising a first semiconductor material on the substrate and forming an insulating layer comprising a cavity structure on the first semiconductor device. The cavity structure comprises at least one growth channel and the growth channel connects a crystalline seed surface of the first semiconductor device with an opening. Further steps include growing via the opening from the seed surface a semiconductor filling structure comprising a second semiconductor material different from the first semiconductor material in the growth channel; forming a semiconductor starting structure for a second semiconductor device from the filling structure; and fabricating a second semiconductor device comprising the starting structure. The invention is notably also directed to corresponding semiconductor circuits.Type: GrantFiled: February 25, 2016Date of Patent: July 11, 2017Assignee: International Business Machines CorporationInventors: Daniele Caimi, Lukas Czornomaz, Veeresh Deshpande, Vladimir Djara, Jean Fompeyrine
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Patent number: 9696488Abstract: A semiconductor structure is provided, the semiconductor structure comprising: a semiconductor substrate processed to comprise at least an optical aspect comprising at least a silicon photonics device and at least an electronic aspect comprising at least an electronic device; at least an interlayer dielectric layer provided on the semiconductor substrate, and at least an electrically interconnecting layer provided on the interlayer dielectric layer, wherein: the semiconductor structure further comprises at least a functional-oxide crystalline layer provided in relation to the interlayer dielectric layer before the interconnecting layer is provided on the interlayer dielectric layer, the functional-oxide crystalline layer comprising at least a functional-oxide material and is processed to comprise at least an active optical device, and the interlayer dielectric layer comprises a first surface and a second surface, the first surface being in common to at least a respective part of the optical aspect and the eleType: GrantFiled: November 19, 2015Date of Patent: July 4, 2017Assignee: International Business Machines CorporationInventors: Stefan Abel, Jean Fompeyrine, Chiara Marchiori
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Patent number: 9673104Abstract: A first channel structure includes SixGe1-x and a second channel structure includes a group III-V compound material. First and second gate stacks are formed on the first and second channel structures. An insulating layer is formed on the gate stacks and the channel structures and is removed from the first channel structure to form a spacer on sidewalls of the first gate stack. First raised source and drain layers are formed on the first channel structure. The insulating layer is removed from the second channel structure to form a spacer on sidewalls of the second gate stack. The surfaces of the first and second channel structures and first source and drain layers are oxidized. The oxide layers are treated by a cleaning process that selectively removes the second native oxide layer only. Second raised source and drain layers are formed on the second channel structure. A CMOS structure is disclosed.Type: GrantFiled: February 10, 2016Date of Patent: June 6, 2017Assignee: International Business Machines CorporationInventors: Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vladimir Djara, Jean Fompeyrine
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Patent number: 9640394Abstract: Method for fabricating a semiconductor structure. The method includes: providing a crystalline silicon substrate; defining an opening in a dielectric layer on the crystalline silicon substrate, the opening having sidewalls and a bottom wherein the bottom corresponds to a surface of the crystalline silicon substrate; providing a confinement structure above the dielectric layer, thereby forming a confinement region between the confinement structure and the dielectric layer; and growing a crystalline compound semiconductor material in the confinement region thereby at least partially filling the confinement region. The present invention also provides an improved compound semiconductor structure and a device for fabricating such semiconductor structure.Type: GrantFiled: August 26, 2015Date of Patent: May 2, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniele Caimi, Lukas Czornomaz, Jean Fompeyrine, Emanuele Uccelli
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Publication number: 20170116514Abstract: A neuromorphic network includes a first node configured to transmit a first optical signal and a second node configured to transmit a second optical signal. A waveguide optically connects the first node to the second node. An integrated optical synapse is located on the waveguide between the first node and the second node, the optical synapse configured to change an optical property based on the first optical signal and the second optical signal such that if a correlation between the first optical signal and the second optical signal is strong, the optical connection between the first node and the second node is increased and if the correlation between the first optical signal and the second optical signal is weak, the optical connection between the first node and the second node is decreased.Type: ApplicationFiled: October 26, 2015Publication date: April 27, 2017Inventors: Stefan Abel, Lukas Czomomaz, Veeresh V. Deshpande, Jean Fompeyrine
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Publication number: 20170116515Abstract: A reservoir computing neuromorphic network includes an input layer comprising one or more input nodes, a reservoir layer comprising a plurality of reservoir nodes, and an output layer comprising one or more output nodes. A portion of at least one of the input layer, the reservoir layer, and the output layer includes an optically tunable material.Type: ApplicationFiled: October 26, 2015Publication date: April 27, 2017Inventors: Stefan Abel, Lukas Czomomaz, Veeresh V. Deshpande, Jean Fompeyrine
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Publication number: 20170097468Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a processed semiconductor substrate. The processed semiconductor substrate includes active electronic components. The semiconductor structure also includes a dielectric layer that covers, at least partially, the processed semiconductor substrate. An interface layer that is suitable for growing optically active material on the interface layer is bonded to the dielectric layer. An optical gain layer and the processed semiconductor substrate are connected through the dielectric layer by electric and/or optical contacts.Type: ApplicationFiled: December 15, 2016Publication date: April 6, 2017Inventors: Lukas Czornomaz, Jean Fompeyrine, Jens Hofrichter, Bert Jan Offrein, Mirja Richter
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Patent number: 9564452Abstract: A method is disclosed for fabricating a semiconductor circuit. A semiconductor substrate is provided. A first semiconductor device is fabricated including a first semiconductor material on the substrate and forming an insulating layer including a cavity structure on the first semiconductor device. The cavity structure includes at least one growth channel and the growth channel connects a crystalline seed surface of the first semiconductor device with an opening. Further steps include growing via the opening from the seed surface a semiconductor filling structure including a second semiconductor material different from the first semiconductor material in the growth channel, forming a semiconductor starting structure for a second semiconductor device from the filling structure, and fabricating a second semiconductor device including the starting structure. Corresponding semiconductor circuits are also disclosed.Type: GrantFiled: February 1, 2016Date of Patent: February 7, 2017Assignee: International Business Machines CorporationInventors: Daniele Caimi, Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vladimir Djara, Jean Fompeyrine
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Publication number: 20170011913Abstract: Method for fabricating a semiconductor structure. The semiconductor structure includes: a crystalline silicon substrate; a dielectric layer on the crystalline silicon substrate, the opening having an opening with sidewalls and a bottom wherein the bottom corresponds to a surface of the crystalline silicon substrate; and a crystalline compound semiconductor layer thereby forming a processable crystalline compound semiconductor substrate, wherein the bottom of the opening is isolated from the crystalline compound material.Type: ApplicationFiled: September 26, 2016Publication date: January 12, 2017Applicant: International Business Machines CorporationInventors: Daniele Caimi, Lukas Czornomaz, Jean Fompeyrine, Emanuele Uccelli
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Patent number: 9515090Abstract: A method includes providing a structure having a substrate, a first insulating layer on the substrate, a first semiconductor material layer on the first insulating layer, a second insulating layer on the first semiconductor layer in a first portion of the structure and a second semiconductor layer of a second, different semiconductor material on the second insulating layer in the first portion. The method further includes growing additional first semiconductor material on the first semiconductor layer in a second portion of the structure forming a regrown semiconductor layer; forming first fins in the regrown semiconductor layer and second fins in the second semiconductor layer; and forming gate structures upon the first and second fins. A height difference, relative to a surface of the first insulating layer, of the gate structures formed upon the first fins and the gate structures formed upon the second fins is less than a predetermined value.Type: GrantFiled: June 9, 2015Date of Patent: December 6, 2016Assignee: International Business Machines CorporationInventors: Daniele Caimi, Lukas Czornomaz, Jean Fompeyrine, Effendi Leobandung
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Publication number: 20160334574Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a processed semiconductor substrate. The processed semiconductor substrate includes active electronic components. The semiconductor structure also includes a dielectric layer that covers, at least partially, the processed semiconductor substrate. An interface layer that is suitable for growing optically active material on the interface layer is bonded to the dielectric layer. An optical gain layer and the processed semiconductor substrate are connected through the dielectric layer by electric and/or optical contacts.Type: ApplicationFiled: November 27, 2013Publication date: November 17, 2016Inventors: Lukas CZORNOMAZ, Jean FOMPEYRINE, Jens HOFRICHTER, Bert Jan OFFREIN, Mirja RICHTER
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Publication number: 20160254147Abstract: A method for fabricating semiconductor structure comprises the steps of providing a substrate including a first crystalline semiconductor material, patterning an opening in a dielectric layer above the substrate, the opening having a bottom, forming a crystalline interlayer on the substrate at least partially covering the bottom, and growing a second crystalline semiconductor material on the crystalline interlayer thereby at least partially filling the opening. The crystalline semiconductor materials are lattice mismatched, and the crystalline interlayer comprises an oxygen compound.Type: ApplicationFiled: May 9, 2016Publication date: September 1, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Stefan Abel, Lukas Czornomaz, Jean Fompeyrine, Mario El Kazzi
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Publication number: 20160139335Abstract: A semiconductor structure is provided, the semiconductor structure comprising: a semiconductor substrate processed to comprise at least an optical aspect comprising at least a silicon photonics device and at least an electronic aspect comprising at least an electronic device; at least an interlayer dielectric layer provided on the semiconductor substrate, and at least an electrically interconnecting layer provided on the interlayer dielectric layer, wherein: the semiconductor structure further comprises at least a functional-oxide crystalline layer provided in relation to the interlayer dielectric layer before the interconnecting layer is provided on the interlayer dielectric layer, the functional-oxide crystalline layer comprising at least a functional-oxide material and is processed to comprise at least an active optical device, and the interlayer dielectric layer comprises a first surface and a second surface, the first surface being in common to at least a respective part of the optical aspect and the eleType: ApplicationFiled: November 19, 2015Publication date: May 19, 2016Inventors: Stefan Abel, Jean Fompeyrine, Chiara Marchiori
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Patent number: 9337265Abstract: A semiconductor structure comprises a substrate comprising a first crystalline semiconductor material, a dielectric layer, above the substrate, defining an opening, a second crystalline semiconductor material at least partially filling the opening, and a crystalline interlayer between the substrate and the second crystalline semiconductor material. The first crystalline semiconductor material and the second crystalline semiconductor material are lattice mismatched, and the crystalline interlayer comprises an oxygen compound. A method for fabricating semiconductor structure comprises the steps of providing a substrate including a first crystalline semiconductor material, patterning an opening in a dielectric layer above the substrate, the opening having a bottom, forming a crystalline interlayer on the substrate at least partially covering the bottom, and growing a second crystalline semiconductor material on the crystalline interlayer thereby at least partially filling the opening.Type: GrantFiled: August 25, 2014Date of Patent: May 10, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Stefan Abel, Lukas Czornomaz, Jean Fompeyrine, Mario El Kazzi
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Publication number: 20160064284Abstract: Method for fabricating a semiconductor structure. The method includes: providing a crystalline silicon substrate; defining an opening in a dielectric layer on the crystalline silicon substrate, the opening having sidewalls and a bottom wherein the bottom corresponds to a surface of the crystalline silicon substrate; providing a confinement structure above the dielectric layer, thereby forming a confinement region between the confinement structure and the dielectric layer; and growing a crystalline compound semiconductor material in the confinement region thereby at least partially filling the confinement region. The present invention also provides an improved compound semiconductor structure and a device for fabricating such semiconductor structure.Type: ApplicationFiled: August 26, 2015Publication date: March 3, 2016Inventors: Daniele Caimi, Lukas Czornomaz, Jean Fompeyrine, Emanuele Uccelli
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Patent number: 9252157Abstract: A method includes providing a structure having a substrate, a first electrically insulating layer overlying the substrate, a first semiconductor layer comprised of a first semiconductor material overlying the first electrically insulating layer, a second electrically insulating layer overlying the first semiconductor layer in a first portion of the structure and a second semiconductor layer comprised of a second, different semiconductor material overlying the second electrically insulating layer in the first portion. The method further includes growing additional first semiconductor material on the first semiconductor layer in a second portion of the structure to form a regrown semiconductor layer; forming fins; forming gate structures orthogonal to the fins and removing at least a portion of the first semiconductor layer in the first portion of the structure to form a void and filling the void with insulating material. Structures formed by the method are also disclosed.Type: GrantFiled: May 13, 2015Date of Patent: February 2, 2016Assignee: International Business Machines CorporationInventors: Lukas Czornomaz, Jean Fompeyrine, Effendi Leobandung
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Publication number: 20150270289Abstract: A method includes providing a structure having a substrate, a first insulating layer on the substrate, a first semiconductor material layer on the first insulating layer, a second insulating layer on the first semiconductor layer in a first portion of the structure and a second semiconductor layer of a second, different semiconductor material on the second insulating layer in the first portion. The method further includes growing additional first semiconductor material on the first semiconductor layer in a second portion of the structure forming a regrown semiconductor layer; forming first fins in the regrown semiconductor layer and second fins in the second semiconductor layer; and forming gate structures upon the first and second fins. A height difference, relative to a surface of the first insulating layer, of the gate structures formed upon the first fins and the gate structures formed upon the second fins is less than a predetermined value.Type: ApplicationFiled: June 9, 2015Publication date: September 24, 2015Inventors: Daniele Caimi, Lukas Czornomaz, Jean Fompeyrine, Effendi Leobandung