Patents by Inventor Jefferson Talledo

Jefferson Talledo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10347569
    Abstract: Embodiments of the present disclosure are directed to leadframes having the cantilevered extension that includes an integral support on the end of the lead nearest the die pad. A support integral to the leadframe allows the support to be built to the proper height to support the cantilevered lead in each package and reduces or eliminates the upward, downward, and side to side deflections caused or allowed by supports built-in to the tooling of the manufacturing equipment. Also, by building the support into the leadframe, the leadframes may be pretaped prior to the die attach and wire bonding steps of the manufacturing process.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: July 9, 2019
    Assignee: STMicroelectronics, Inc.
    Inventor: Jefferson Talledo
  • Publication number: 20190198454
    Abstract: A leadframe having extensions around an outer edge of a die pad are disclosed. More specifically, leadframes are created with a flange formed at the outer edge of the die pad and extending away from the die pad. The flange is bent, such that it is positioned at an angle with respect to the die pad. Leadframes are also created with anchoring posts formed adjacent the outer edge of the die pad and extending away from the die pad. The anchoring posts have a central thickness that is less than a thickness of first and second portions opposite the central portion. When the leadframe is incorporated into a package, molding compound completely surrounds each flange or anchoring post, which increases the bond strength between the leadframe and the molding compound due to increased contact area. The net result is a reduced possibility of delamination at edges of the die pad.
    Type: Application
    Filed: December 18, 2018
    Publication date: June 27, 2019
    Inventor: Jefferson TALLEDO
  • Publication number: 20190096789
    Abstract: The present disclosure is directed to a semiconductor die on a tapeless leadframe and covered in encapsulant. The semiconductor package includes leads formed from the leadframe and electrically coupled to the semiconductor die, the leads being accessible through electrical contacts embedded in the encapsulant. Openings between the leads and the leadframe are formed from etching recesses from opposing sides of the leadframe. The resulting openings have non-uniform sidewalls. The leadframe is further electrically or thermally coupled to electrical contacts embedded in the encapsulant. The embedded electrical contacts forming a land grid array.
    Type: Application
    Filed: November 28, 2018
    Publication date: March 28, 2019
    Inventor: Jefferson Talledo
  • Publication number: 20190074241
    Abstract: The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.
    Type: Application
    Filed: October 29, 2018
    Publication date: March 7, 2019
    Inventors: Jefferson Talledo, Tito Mangaoang
  • Patent number: 10204814
    Abstract: According to principles as taught herein, a leadframe array for a semiconductor die is prepared having locations to receive solder balls. Solder balls are then applied to the leadframe array, after which the leadframe array and solder ball combination is placed in a first mold and encased in a first molding compound. After the molding compound is cured, a layer of molding compound is removed to expose the solder balls. After this, a semiconductor die is electrically connected to the exposed solder balls. The combined semiconductor die and leadframe are placed in a second mold, and a second molding compound injected. The second molding compound flows around the semiconductor die and leadframe combination, fully enclosing the electrical connections between the leadframe and the semiconductor die, making the final package a twice-molded configuration. After this, the twice-molded semiconductor package array is cut at the appropriate locations to singulate the packages into individual products.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: February 12, 2019
    Assignee: STMicroelectronics, Inc.
    Inventor: Jefferson Talledo
  • Publication number: 20190043790
    Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.
    Type: Application
    Filed: October 8, 2018
    Publication date: February 7, 2019
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
  • Publication number: 20190035669
    Abstract: According to principles as taught herein, a leadframe array for a semiconductor die is prepared having locations to receive solder balls. Solder balls are then applied to the leadframe array, after which the leadframe array and solder ball combination is placed in a first mold and encased in a first molding compound. After the molding compound is cured, a layer of molding compound is removed to expose the solder balls. After this, a semiconductor die is electrically connected to the exposed solder balls. The combined semiconductor die and leadframe are placed in a second mold, and a second molding compound injected. The second molding compound flows around the semiconductor die and leadframe combination, fully enclosing the electrical connections between the leadframe and the semiconductor die, making the final package a twice-molded configuration. After this, the twice-molded semiconductor package array is cut at the appropriate locations to singulate the packages into individual products.
    Type: Application
    Filed: July 28, 2017
    Publication date: January 31, 2019
    Inventor: Jefferson TALLEDO
  • Publication number: 20190006266
    Abstract: According to principles of the disclosure as explained herein, selected leads are electrically connected through metal strips to the lead frame until the end of the manufacturing process. The lead frame is grounded through the manufacturing process to prevent any ESD event from causing damage to the protected leads. In the final singulation step, the leads are electrically isolated from each other and from the lead frame, thus maintaining protection from a potential ESD event up until the final package singulation step.
    Type: Application
    Filed: June 28, 2017
    Publication date: January 3, 2019
    Inventors: Frederick Ray GOMEZ, Tito MANGAOANG, JR., Jefferson TALLEDO
  • Patent number: 10147673
    Abstract: The present disclosure is directed to a semiconductor die on a tapeless leadframe and covered in encapsulant. The semiconductor package includes leads formed from the leadframe and electrically coupled to the semiconductor die, the leads being accessible through electrical contacts embedded in the encapsulant. Openings between the leads and the leadframe are formed from etching recesses from opposing sides of the leadframe. The resulting openings have non-uniform sidewalls. The leadframe is further electrically or thermally coupled to electrical contacts embedded in the encapsulant. The embedded electrical contacts forming a land grid array.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 4, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo
  • Patent number: 10141246
    Abstract: The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: November 27, 2018
    Assignee: STMicroelectronics, Inc.
    Inventors: Jefferson Talledo, Tito Mangaoang
  • Patent number: 10109563
    Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: October 23, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
  • Publication number: 20180286789
    Abstract: The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.
    Type: Application
    Filed: April 12, 2018
    Publication date: October 4, 2018
    Inventors: Jefferson TALLEDO, Tito MANGAOANG
  • Publication number: 20180204786
    Abstract: The present disclosure is directed to a die having a metallized sidewall and methods of manufacturing the same. A contiguous metal layer is applied to each edge of a backside of a wafer. The wafer is cut at a base of a plurality of channels formed in the backside to create individual die each having a flange that is part of a sidewall of the die and includes a portion that is covered by the metal layer. When an individual die is coupled to a die pad, a semiconductive glue bonds the metal layer on the sidewall and a backside of the die to the die pad, which decreases the risk of delamination along the sides of the die. The flange also prevents the glue from contacting the active side of the die by acting as a barrier against adhesive creep of the glue up the sidewall of the die.
    Type: Application
    Filed: January 18, 2017
    Publication date: July 19, 2018
    Inventors: Rennier RODRIGUEZ, Aiza Marie AGUDON, Jefferson TALLEDO
  • Publication number: 20180197809
    Abstract: A semiconductor device may include a circuit board having an opening, and a frame. The frame may have an IC die pad in the opening, and arms extending outwardly from the IC die pad and coupled to the circuit board. The semiconductor device may include an IC mounted on the IC die pad, bond wires coupling the circuit board with the IC, and encapsulation material surrounding the IC, the bond wires, and the arms.
    Type: Application
    Filed: March 5, 2018
    Publication date: July 12, 2018
    Inventors: Jefferson Talledo, Rammil Seguido
  • Publication number: 20180190576
    Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.
    Type: Application
    Filed: January 5, 2017
    Publication date: July 5, 2018
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
  • Patent number: 10008472
    Abstract: A method is for making a semiconductor device. The method may include providing a lead frame having a recess, forming a sacrificial material in the recess of the lead frame, and mounting an IC on the lead frame. The method may include encapsulating the IC and the lead frame, removing portions of the lead frame to define lead frame contacts for the IC, and removing the sacrificial material to define for each lead frame contact a solder anchoring tab extending outwardly at a lower region and defining a sidewall recess between opposing portions of the solder anchoring tab and the encapsulation material.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: June 26, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo
  • Publication number: 20180144952
    Abstract: One or more embodiments are directed to semiconductor packages with one or more cantilever pads and methods of making same. In one embodiment a recess is located in a substrate of the package facing the cantilever pad. The cantilever pad includes a conductive pad on which a conductive ball is formed. The cantilever pad is configured to absorb stresses acting on the package.
    Type: Application
    Filed: January 19, 2018
    Publication date: May 24, 2018
    Inventors: Jefferson Talledo, Godfrey Dimayuga
  • Patent number: 9972558
    Abstract: The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: May 15, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Jefferson Talledo, Tito Mangaoang
  • Publication number: 20180130767
    Abstract: A method is for making a semiconductor device. The method may include providing a lead frame having a recess, forming a sacrificial material in the recess of the lead frame, and mounting an IC on the lead frame. The method may include encapsulating the IC and the lead frame, removing portions of the lead frame to define lead frame contacts for the IC, and removing the sacrificial material to define for each lead frame contact a solder anchoring tab extending outwardly at a lower region and defining a sidewall recess between opposing portions of the solder anchoring tab and the encapsulation material.
    Type: Application
    Filed: January 5, 2018
    Publication date: May 10, 2018
    Inventor: Jefferson Talledo
  • Patent number: 9947636
    Abstract: A method for making a semiconductor device may include bonding a top lead frame component, having recesses, with a bottom lead frame component to form a lead frame, the top and bottom lead frame components each including metal. The method may include mounting an IC on the lead frame, encapsulating the IC and the lead frame, and removing portions of the bottom lead frame component to define contacts for the IC.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: April 17, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo