Abstract: Disclosed herein are embodiments of electronic package incorporating a thermal interface material (e.g., a metal TIM) that is positioned between a lid and a chip on a substrate. The TIM has a predetermined (i.e., repeatable) minimum thickness and is further registered to the top surface of the chip (i.e., the TIM has an essentially symmetric shape and does not extend vertically along the sidewalls of the chip). Also, disclosed herein are embodiments of a method of forming such an electronic package that uses a hierarchical heating process that cures a lid sealant, thereby securing the lid to the substrate, and then reflows (i.e., melts and cools) the TIM, thereby adhering the TIM to both the chip and lid. This hierarchical heating process ensures that the TIM has the above-mentioned characteristics (i.e., a predetermined minimum thickness and registration to the top surface of the chip) and further provides robust process windows for high-yield, low-cost electronic package manufacturing.

Abstract: A method attaches a semiconductor chip to a substrate, applies a thermal interface material to a top of the semiconductor chip, and positions a lid over the semiconductor chip typically attached to the substrate with an adhesive. The method applies a force near the distal ends of the lid or substrate to cause a center portion of the lid or substrate to bow away from the semiconductor chip and increases the central thickness of the thermal interface material prior to curing. While the center portion of the lid or substrate is bowed away from the semiconductor chip, the thermal interface material method increases the temperature of the assembly, thus curing the thermal interface material and lid adhesive.

Abstract: A method attaches a semiconductor chip to a substrate, applies a thermal interface material to a top of the semiconductor chip, and positions a lid over the semiconductor chip typically attached to the substrate with an adhesive. The method applies a force near the distal ends of the lid or substrate to cause a center portion of the lid or substrate to bow away from the semiconductor chip and increases the central thickness of the thermal interface material prior to curing. While the center portion of the lid or substrate is bowed away from the semiconductor chip, the thermal interface material method increases the temperature of the assembly, thus curing the thermal interface material and lid adhesive.

Abstract: An apparatus to reduce a thermal penalty of a three-dimensional (3D) die stack for use in a computing environment is provided and includes a substrate installed within the computing environment, a first component to perform operations of the computing environment, which is coupled to the substrate in a stacking direction, a set of second components to perform operations of the computing environment, each of which is coupled to the first component and segmented with respect to one another to form a vacated region, a thermal interface material (TIM) disposed on exposed surfaces of the first and second components, and a lid, including a protrusion, coupled to the substrate to overlay the first and second components such that the protrusion extends into the vacated region and such that surfaces of the lid and the protrusion thermally communicate with the first and second components via the TIM.

Abstract: Disclosed herein are embodiments of electronic package incorporating a thermal interface material (e.g., a metal TIM) that is positioned between a lid and a chip on a substrate. The TIM has a predetermined (i.e., repeatable) minimum thickness and is further registered to the top surface of the chip (i.e., the TIM has an essentially symmetric shape and does not extend vertically along the sidewalls of the chip). Also, disclosed herein are embodiments of a method of forming such an electronic package that uses a hierarchical heating process that cures a lid sealant, thereby securing the lid to the substrate, and then reflows (i.e., melts and cools) the TIM, thereby adhering the TIM to both the chip and lid. This hierarchical heating process ensures that the TIM has the above-mentioned characteristics (i.e., a predetermined minimum thickness and registration to the top surface of the chip) and further provides robust process windows for high-yield, low-cost electronic package manufacturing.

Abstract: An IC chip package and related method are disclosed. The IC chip package may include a printed circuit board (PCB) coupled to a chip carrier by a land grid array (LGA) connector; a metal stiffener including at least one force-adjustable member contacting an underside of the PCB; and at least two couplers for coupling the metal stiffener to a lid or a heat sink, with the PCB, the chip carrier and the LGA connector therebetween. The force-adjustable member reduces the required assembly forces and accommodates natural and non-systematic out-of flatness tolerances of the PCB and the chip carrier.

Abstract: An electronic module and a method of assembling the electronic module. A circuit board is connected to a chip substrate by an array of connectors, and a base member is on the side of the circuit board away from the chip substrate and connector array. An elastomeric structure is placed between the circuit board and the base member. The elastomeric structure has voids between a first defining plane adjacent the circuit board and a second defining plane adjacent the base member, with the voids adapted to permit local deformation of elastomeric material in the structure. The method includes applying a compressive force between the circuit board and base member to at least partially compressing the elastomeric structure to improve load equalization on the circuit board.

Abstract: An IC chip package and related method are disclosed. The IC chip package may include a printed circuit board (PCB) coupled to a chip carrier by a land grid array (LGA) connector; a metal stiffener including at least one force-adjustable member contacting an underside of the PCB; and at least two couplers for coupling the metal stiffener to a lid or a heat sink, with the PCB, the chip carrier and the LGA connector therebetween. The force-adjustable member reduces the required assembly forces and accommodates natural and non-systematic out-of flatness tolerances of the PCB and the chip carrier.

Abstract: Apparatus and methods are provided for thermally coupling a semiconductor chip directly to a heat conducting device (e.g., a copper heat sink) using a thermal joint that provides increased thermal conductivity between the heat conducting device and high power density regions of the semiconductor chip, while minimizing or eliminating mechanical stress due to the relative displacement due to the difference in thermal expansion between the semiconductor chip and the heat conducting device.

Abstract: A chip package including a chip extension for containing thermal interface material (TIM) and improves chip cooling, and a related method, are disclosed. In particular, the chip package includes a chip, a cooling structure coupled to the chip via a TIM, and a chip extension may be thermally coupled to an outer edge of the chip. A TIM placed between the chip and the cooling structure is contained during thermal cycling by the chip extension such that void formation at the edge of the chip, which can move between the chip and cooling structure, is suppressed. The chip extension also improves lateral heat dissipation by providing a greater thermal contact area between the cooling structure and the chip and, if needed, the substrate at a much lower cost than using larger die with lower production unit output from a wafer.

Abstract: An electronic module and a method of assembling the electronic module. A circuit board is connected to a chip substrate by an array of connectors, and a base member is on the side of the circuit board away from the chip substrate and connector array. An elastomeric structure is placed between the circuit board and the base member. The elastomeric structure has voids between a first defining plane adjacent the circuit board and a second defining plane adjacent the base member, with the voids adapted to permit local deformation of elastomeric material in the structure. The method includes applying a compressive force between the circuit board and base member to at least partially compressing the elastomeric structure to improve load equalization on the circuit board.

Abstract: A chip package including a chip extension for containing thermal interface material (TIM) and improves chip cooling, and a related method, are disclosed. In particular, the chip package includes a chip, a cooling structure coupled to the chip via a TIM, and a chip extension may be thermally coupled to an outer edge of the chip. A TIM placed between the chip and the cooling structure is contained during thermal cycling by the chip extension such that void formation at the edge of the chip, which can move between the chip and cooling structure, is suppressed. The chip extension also improves lateral heat dissipation by providing a greater thermal contact area between the cooling structure and the chip and, if needed, the substrate at a much lower cost than using larger die with lower production unit output from a wafer.

Abstract: The present invention relates generally to apparatus and methods for cooling semiconductor integrated circuit (IC) chip package structures. More specifically, the present invention relates to apparatus and methods for thermally coupling semiconductor chips to a heat conducting device (e.g., copper thermal hat or lid) using a compliant thermally conductive material (e.g., thermal paste), wherein a thermal interface is designed to prevent/inhibit the formation of voids in the compliant thermally conductive material due to the flow of such material in and out from between the chips and the heat conducting device due to thermal cycling.

Abstract: A system and method to form a reworkable compression seal between an electronic module and a cap are disclosed. The system and method include an electronic module having a tapered edge configured on at least a portion of the edge defining a perimeter of the electronic module and the cap configured with an opening to receive the electronic module therein. A compression seal is disposed with the cap and is configured to surround one or more chips or other electronic components on the electronic module to form a seal between the electronic module and the cap. A plurality of side loaders are operably coupled to the cap and aligned to receive the tapered edge on the electronic module. Each side loader is configured to engage the tapered edge and provide sufficient compressive force to the compression seal disposed between the electronic module and the cap.

Abstract: Apparatus and methods are provided for thermally coupling a semiconductor chip directly to a heat conducting device (e.g., a copper heat sink) using a thermal joint that provides increased thermal conductivity between the heat conducting device and high power density regions of the semiconductor chip, while minimizing or eliminating mechanical stress due to the relative displacement due to the difference in thermal expansion between the semiconductor chip and the heat conducting device.

Abstract: A system and method to form a reworkable compression seal between an electronic module and a cap are disclosed. The system and method include an electronic module having a tapered edge configured on at least a portion of the edge defining a perimeter of the electronic module and the cap configured with an opening to receive the electronic module therein. A compression seal is disposed with the cap and is configured to surround one or more chips or other electronic components on the electronic module to form a seal between the electronic module and the cap. A plurality of side loaders are operably coupled to the cap and aligned to receive the tapered edge on the electronic module. Each side loader is configured to engage the tapered edge and provide sufficient compressive force to the compression seal disposed between the electronic module and the cap.

Abstract: A high power density thermal packaging solution. A highly efficient thermal path is provided using a lid of a unique design configuration that connects the chip back-side to both a heat sink and thermally conductive substrate vias thus establishing two thermal paths to carry heat from the die. The thermal interface between the chip back-side to lid and lid-to-substrate is enhanced with a thermally conductive elastomer. The heat is conducted through the substrate through thermal vias that are added to the perimeter of the substrate or which may be configured from preexisting electrical shielding structures that connect the top surface of the substrate to the bottom of the package. The bottom surface connection then conducts the heat to a copper ground plane in the printed circuit card. The heat from the die to the heat sink is transferred in the conventional method using the thin layer of thermally conductive elastomer to complete the thermal path from chip to lid to heat sink.

Abstract: A ring shaped pressure plate is provided in a socket and land grid array module assembly for urging the module into electrical contact. The ring shaped pressure plate is not only readily removable but it also engages a land grid array module in a fashion which reduces stress to chip, chip underfill, chip lid, and chip thermal paste structures. In an alternate embodiment of the present invention, pressure is applied in a similar manner except that lockably engageable arms supporting pressure rails on opposite sides of the module are employed. Both embodiments reduce stress and provide a land grid array engagement mechanism which is readily removable and which also provide a central opening or central portion access to chip module components for purposes of cooling such as by providing direct attachment to heat sinks or indirect attachment to heat sinks through heat spreaders.

Abstract: The present invention relates generally to a new apparatus and method for directly joining a chip to a heat sink. More particularly, the invention encompasses an apparatus and a method that uses a double-sided, pressure-sensitive, thermally-conductive adhesive tape to directly join a chip or similar such device to a heat sink.

Abstract: The present invention relates generally to a new apparatus and method for a chip carrier. More particularly, the invention encompasses an apparatus and a method that uses a chip carrier having a single encapsulant to provide both flip chip fatigue life enhancement and environmental protection. A double-sided, pressure-sensitive, thermally-conductive adhesive tape could also be used with the encapsulated chip to directly attach the chip to a heat sink. Similarly, also disclosed is a method and apparatus for directly joining a heat sink to the chip carrier.