Patents by Inventor Jeffrey D. Chinn

Jeffrey D. Chinn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6802933
    Abstract: This invention is directed to a method for etching films on semiconductor substrates and cleaning etch chambers. The method includes an improved processing sequence and cleaning method where residue formed from processing a previous substrate are cleaned by the etching process used to remove an exposed layer of material from the present substrate. The process provides improved substrate throughput by combining the step to clean residue from a previous substrate with an etch step conducted on the present substrate. Applicants have found the method particularly useful in processing structures such as DRAM stacks, especially where the residue is formed by a trench etched in the previous silicon substrate and the exposed layer etched from the present substrate is silicon nitride.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: October 12, 2004
    Inventors: Anisul Khan, Ajay Kumar, Jeffrey D. Chinn, Dragan Podlesnik
  • Publication number: 20040087054
    Abstract: Disclosed are methods of plasma etching through a substrate while preventing rapid leakage of heat transfer fluid during the etch process, protecting process chamber hardware underlying said substrate, and separating components within said substrate while maintaining said components in a position relative to other components within said substrate. The method involves application of a disposable protective barrier layer to the backside of the substrate prior to etching and then removing the barrier layer subsequent to etching.
    Type: Application
    Filed: October 18, 2002
    Publication date: May 6, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Jeffrey D. Chinn, Rolf A. Guenther, Michael B. Rattner, James A. Cooper
  • Publication number: 20040060906
    Abstract: A chemical-mechanical jet etching method rapidly removes large amounts of material in wafer thinning, or produces large-scale features on a silicon wafer, gallium arsenide substrate, or similar flat semiconductor workpiece, at etch rates in the range of 10-100 microns of workpiece thickness per minute. A nozzle or array of nozzles, optionally including a dual-orifice nozzle, delivers a high-pressure jet of machining etchant fluid to the surface of the workpiece. The machining etchant comprises a liquid or gas, carrying particulate material. The liquid may be a chemical etchant, or a solvent for a chemical etchant, if desired. The areas which are not to be etched may be shielded from the jet by a patterned mask, or the jet may be directed at areas from which material is to be removed, as in wafer thinning or direct writing, depending on the size of the desired feature or etched area.
    Type: Application
    Filed: September 30, 2003
    Publication date: April 1, 2004
    Inventors: Robert Z. Bachrach, Jeffrey D. Chinn
  • Publication number: 20040053505
    Abstract: Disclosed herein is an easy and well-integrated method of etching features to different depths in a crystalline substrate, such as a single-crystal silicon substrate. The method utilizes a specialized masking process and takes advantage of a highly selective etch process. The method provides a system of interconnected, variable depth reservoirs and channels. The plasma used to etch the channels may be designed to provide a sidewall roughness of about 200 nm or less. The resulting structure can be used in various MEMS applications, including biomedical MEMS and MEMS for semiconductor applications.
    Type: Application
    Filed: September 18, 2002
    Publication date: March 18, 2004
    Inventors: Jeffrey D. Chinn, Michael B. Rattner, James A. Cooper, Rolf A. Guenther
  • Patent number: 6699356
    Abstract: A chemical-mechanical jet etching method rapidly removes large amounts of material in wafer thinning, or produces large-scale features on a silicon wafer, gallium arsenide substrate, or similar flat semiconductor workpiece, at etch rates in the range of 10-100 microns of workpiece thickness per minute. A nozzle or array of nozzles, optionally including a dual-orifice nozzle, delivers a high-pressure jet of machining etchant fluid to the surface of the workpiece. The machining etchant comprises a liquid or gas, carrying particulate material. The liquid may be a chemical etchant, or a solvent for a chemical etchant, if desired. The areas which are not to be etched may be shielded from the jet by a patterned mask, or the jet may be directed at areas from which material is to be removed, as in wafer thinning or direct writing, depending on the size of the desired feature or etched area.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: March 2, 2004
    Assignee: Applied Materials, Inc.
    Inventors: Robert Z. Bachrach, Jeffrey D. Chinn
  • Publication number: 20040033639
    Abstract: Disclosed herein is a method of improving the adhesion of a hydrophobic self-assembled monolayer (SAM) coating to a surface of a MEMS structure, for the purpose of preventing stiction. The method comprises treating surfaces of the MEMS structure with a plasma generated from a source gas comprising oxygen and, optionally, hydrogen. The treatment oxidizes the surfaces, which are then reacted with hydrogen to form bonded OH groups on the surfaces. The hydrogen source may be present as part of the plasma source gas, so that the bonded OH groups are created during treatment of the surfaces with the plasma. Also disclosed herein is an integrated method for release and passivation of MEMS structures which may be adjusted to be carried out in a either a single chamber processing system or a multi-chamber processing system.
    Type: Application
    Filed: May 9, 2003
    Publication date: February 19, 2004
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Jeffrey D. Chinn, Rolf A. Guenther, Michael B. Rattner, James A. Cooper, Toi Yue Becky Leung, Claes H. Bjorkman
  • Publication number: 20040023508
    Abstract: We have developed an uncomplicated method of plasma etching deeply recessed features such as deep trenches, of at least 5 &mgr;m in depth, in a silicon-containing substrate, in a manner which generates smooth sidewalls, having a roughness of less than about 1 &mgr;m, typically less than about 500 nm, and even more typically between about 100 nm and 20 nm. Features having a sidewall taper angle, relative to an underlying substrate, typically ranges from about 85° to about 92° and exhibiting the smooth sidewalls are produced by the method. In one embodiment, a stabilizing etchant species is used constantly during the plasma etch process, while at least one other etchant species and at least one polymer depositing species are applied intermittently, typically periodically, relative to each other. In another embodiment, the stabilizing etchant species is used constantly and a mixture of the other etchant species and polymer depositing species is used intermittently.
    Type: Application
    Filed: August 2, 2002
    Publication date: February 5, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Jeffrey D. Chinn, Michael Rattner, Nicholas Pornsin-Sirirak, Yanping Li
  • Patent number: 6666979
    Abstract: The present invention pertains to a method of fabricating a surface within a MEM which is free moving in response to stimulation. The free moving surface is fabricated in a series of steps which includes a release method, where release is accomplished by a plasmaless etching of a sacrificial layer material. An etch step is followed by a cleaning step in which by-products from the etch step are removed along with other contaminants which may lead to stiction. There are a series of etch and then clean steps so that a number of “cycles” of these steps are performed. Between each etch step and each clean step, the process chamber pressure is typically abruptly lowered, to create turbulence and aid in the removal of particulates which are evacuated from the structure surface and the process chamber by the pumping action during lowering of the chamber pressure. The final etch/clean cycle may be followed by a surface passivation step in which cleaned surfaces are passivated and/or coated.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: December 23, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Jeffrey D. Chinn, Vidyut Gopal, Sofiane Soukane, Toi Yue Becky Leung
  • Publication number: 20030217693
    Abstract: A substrate support assembly for processing a substrate in a processing chamber comprises a substrate carrier having a bottom surface positioned in contact with a substrate support. The substrate carrier has a recess formed into a top surface. The recess has a support surface and a support region between the bottom surface and the support surface. A shadow ring is positioned proximate the substrate carrier to partially shield the support surface of the substrate carrier.
    Type: Application
    Filed: October 8, 2002
    Publication date: November 27, 2003
    Applicant: Applied Materials, Inc.
    Inventors: Michael B. Rattner, Rolf A. Guenther, Jeffrey D. Chinn
  • Publication number: 20030219986
    Abstract: A substrate carrier for carrying one or more substrates comprises a bottom surface, a top surface opposed to the bottom surface, one or more recesses formed into the top surface, each of the one or more recesses having a support surface that defines a support region for a substrate. The support region is adapted to contact a bottom of the substrate. The support region may have a thickness less than a depth of the one or more recesses. The support region may comprise a porous material to permit thermal fluid to percolate through the support region.
    Type: Application
    Filed: October 8, 2002
    Publication date: November 27, 2003
    Applicant: Applied Materials, Inc.
    Inventors: Michael B. Rattner, Rolf A. Guenther, Jeffrey D. Chinn
  • Patent number: 6653237
    Abstract: Processes for forming trenches within silicon substrates are described. According to an embodiment of the invention, a masked substrate is initially provided that comprises (a) a silicon substrate and (b) a patterned resist layer over the silicon substrate. The patterned resist layer has one or more apertures formed therein. Subsequently, a trench is formed in the substrate through the apertures in the resist layer by an inductive plasma-etching step, which is conducted using plasma source gases that comprise SF6, at least one fluorocarbon gas, and N2. If desired, Cl2 can also be provided in addition to the above source gases. The process of the present invention produces chamber deposits in low amounts, while providing high etching rates, high silicon:resist selectivities, and good trench sidewall profile control.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: November 25, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Shashank Deshmukh, David Mui, Jeffrey D. Chinn, Dragan V Podlesnik
  • Publication number: 20030211752
    Abstract: Disclosed herein is a method of smoothing a trench sidewall after a deep trench silicon etch process which minimizes sidewall scalloping present after the silicon trench etch. The method comprises exposing the silicon trench sidewall to a plasma generated from a fluorine-containing gas, at a process chamber pressure within the range of about 1 mTorr to about 30 mTorr, for a time period within the range of about 10 seconds to about 600 seconds. A substrate bias voltage within the range of about −10 V to about −40 V is applied during the performance of the post-etch treatment method of the invention.
    Type: Application
    Filed: May 1, 2002
    Publication date: November 13, 2003
    Inventors: Michael Rattner, Jeffrey D. Chinn
  • Publication number: 20030207579
    Abstract: Disclosed herein is a method of etching deep trenches in a substrate which utilizes the overlying mask structure to achieve a trench having a positive tapered sidewall angle of less than about 88°. The method employs the successive etching of a lateral undercut in the substrate beneath a masking material, while at the same time etching vertically downward beneath the mask. The coordinated widening of the lateral undercut at the top of the trench, while vertically extending the depth of the trench, is designed to provide the desired trench sidewall taper angle.
    Type: Application
    Filed: May 1, 2002
    Publication date: November 6, 2003
    Inventors: Michael Rattner, Jeffrey D. Chinn
  • Patent number: 6635573
    Abstract: We have discovered a method of detecting the approach of an endpoint during the etching of a material within a recess such as a trench or a contact via. The method provides a clear and distinct inflection endpoint signal, even for areas of a substrate containing isolated features. The method includes etching the material in the recess and using thin film interferometric endpoint detection to detect an endpoint of the etch process, where the interferometric incident light beam wavelength is tailored to the material being etched; the spot size of the substrate illuminated by the light beam is sufficient to provide adequate signal intensity from the material being etched; and the refractive index of the material being etched is sufficiently different from the refractive index of other materials contributing to reflected light from the substrate, that the combination of the light beam wavelength, the spot size, and the difference in refractive index provides a clear and distinct endpoint signal.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: October 21, 2003
    Assignee: Applied Materials, Inc
    Inventors: Wilfred Pau, Meihua Shen, Jeffrey D. Chinn
  • Publication number: 20030190814
    Abstract: A method for plasma etching substrates having high open area patterns is described. The method is useful in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used to etch strict profile control trenches with 89° +/−1° sidewalls on silicon substrates with high open area patterns such as patterns between about 50% and about 90%. The novel method plasma etches high open area substrates using a plasma formed from a gaseous mixture that includes an oxygen source gas, a fluorine source gas and a fluorocarbon source gas. In an alternative embodiment, the fluorocarbon source gas is a passivation gas. In another alternative embodiment, the fluorocarbon source gas consists essentially of a fluorocarbon having fluorine and carbon in a 2:1 ratio. In another particular embodiment, the oxygen source gas is O2, the fluorine source gas is SF6 and the fluorocarbon source gas is C4F8.
    Type: Application
    Filed: May 23, 2002
    Publication date: October 9, 2003
    Applicant: Applied Materials, Inc.
    Inventors: Ajay Kumar, Ansul Khan, Dragan V. Podlesnik, Jeffrey D. Chinn
  • Patent number: 6620575
    Abstract: The present invention pertains to a method for depositing built-up structures on the surface of patterned masking material used for semiconductor device fabrication. Such built-up structures are useful in achieving critical dimensions in the fabricated device. The composition of the built-up structure to be fabricated is dependant upon the plasma etchants used during etching of underlying substrates and on the composition of the substrate material directly underlying the masking material.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: September 16, 2003
    Assignee: Applied Materials, Inc
    Inventors: Nam-Hun Kim, Jeffrey D. Chinn
  • Publication number: 20030166342
    Abstract: Disclosed herein is a method of improving the adhesion of a hydrophobic self-assembled monolayer (SAM) coating to a surface of a MEMS structure, for the purpose of preventing stiction. The method comprises pretreating surfaces of the MEMS structure with a plasma generated from a source gas comprising oxygen and, optionally, hydrogen. The treatment oxidizes the surfaces, which are then reacted with hydrogen to form bonded OH groups on the surfaces. The hydrogen source may be present as part of the plasma source gas, so that the bonded OH groups are created during treatment of the surfaces with the plasma. Also disclosed herein is an integrated method for release and passivation of MEMS structures.
    Type: Application
    Filed: November 20, 2002
    Publication date: September 4, 2003
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Jeffrey D. Chinn, Rolf A. Guenther, Michael B. Rattner, James A. Cooper, Toi Yue Becky Leung
  • Patent number: 6605319
    Abstract: The method of the invention involves depositing a plurality of thin layers of film, each layer having a thickness ranging from about 500Å to about 2000Å. Low Pressure Chemical Vapor Deposition or other techniques known in the art maybe used to deposit each thin layer of film. The film is polysilicon or silicon-germanium, where the germanium content ranges from about 4% by weight to about 20% by weight germanium. A Rapid Thermal Anneal (“RTA”) is performed on a deposited thin film layer to relieve residual film stress in at least that film layer. The use of RTA rather than furnace annealing permits much shorter annealing times. Optionally, but advantageously, hydrogen may be present during RTA to permit the use of lower processing temperatures, typically about 20% lower relative to a customary anneal. A series of film deposition/rapid thermal anneal cycles is used to produce the desired, nominal total thickness polysilicon film.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: August 12, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Jeffrey D. Chinn, Yi-Hsing Chen, Robert Z. Bachrach, John Christopher Moran
  • Patent number: 6599437
    Abstract: A two-step method of etching an organic coating layer, in particular, an organic antireflection coating (ARC) layer, is disclosed. During the main etch step, the organic coating layer is etched using a plasma generated from a first source gas which includes a fluorocarbon and a non-carbon-containing, halogen-comprising gas. Etching is performed using a first substrate bias power. During the overetch step, residual organic coating material remaining after the main etch step is removed by exposing the substrate to a plasma generated from a second source gas which includes a chlorine-containing gas and an oxygen-containing gas, and which does not include a polymer-forming gas. The overetch step is performed using a second substrate bias power which is less than the first substrate bias power.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: July 29, 2003
    Assignee: Applied Materials Inc.
    Inventors: Oranna Yauw, Meihua Shen, Nicolas Gani, Jeffrey D. Chinn
  • Patent number: 6599842
    Abstract: A method for processing a substrate disposed in a substrate processing chamber to modify the contour of a trench formed on the substrate. The substrate processing chamber is the type that has a coil and a plasma generation system including a source power system operatively coupled to the coil and a bias power system operatively coupled to the substrate process chamber. The method includes transferring the substrate into the substrate process chamber. Thereafter, the substrate is exposed to a plasma formed from a first process gas consisting essentially of a sputtering agent by applying RF energy from the source power system to the coil. The plasma is biased toward the substrate by applying bias power to the substrate process chamber. Thereafter, the substrate is exposed to a plasma formed from a second process gas without applying bias power or applying minimal bias power to the substrate process chamber.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: July 29, 2003
    Assignee: Applied Materials, Inc.
    Inventors: John Chao, Mohit Jain, Jeffrey D. Chinn