Patents by Inventor Jeffrey D. Chinn
Jeffrey D. Chinn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20030124848Abstract: A method of determining the time to release of a movable feature in a multilayer substrate of silicon-containing materials including alternate layers of polysilicon and silicon oxide wherein a mass monitoring device determines the mass of a released feature, and the substrate is etched with anhydrous hydrogen fluoride until the substrate mass is equivalent to that of the released movable feature when the etch time is noted. A suitable mass monitoring device is a quartz crystal microbalance.Type: ApplicationFiled: October 8, 2002Publication date: July 3, 2003Applicant: APPLIED MATERIALS, INC.Inventors: Jeffrey D. Chinn, Robert Z. Bachrach
-
Patent number: 6576489Abstract: The invention includes methods of forming microstructure devices. In an exemplary method, a substrate is provided which includes a first material and a second material. At least one of the first and second materials is exposed to vapor-phase alkylsilane-containing molecules to form a coating over the at least one of the first and second materials.Type: GrantFiled: May 7, 2001Date of Patent: June 10, 2003Assignee: Applied Materials, Inc.Inventors: Toi Yue Becky Leung, Jeffrey D. Chinn
-
Publication number: 20030080082Abstract: The present invention pertains to a method of fabricating a surface within a MEM which is free moving in response to stimulation. The free moving surface is fabricated in a series of steps which includes a release method, where release is accomplished by a plasmaless etching of a sacrificial layer material. An etch step is followed by a cleaning step in which by-products from the etch step are removed along with other contaminants which may lead to stiction. There are a series of etch and then clean steps so that a number of “cycles” of these steps are performed. Between each etch step and each clean step, the process chamber pressure is typically abruptly lowered, to create turbulence and aid in the removal of particulates which are evacuated from the structure surface and the process chamber by the pumping action during lowering of the chamber pressure. The final etch/clean cycle may be followed by a surface passivation step in which cleaned surfaces are passivated and/or coated.Type: ApplicationFiled: October 29, 2001Publication date: May 1, 2003Inventors: Jeffrey D. Chinn, Vidyut Gopal, Sofiane Soukane, Toi Yue Becky Leung
-
Publication number: 20030082919Abstract: We have discovered a method of detecting the approach of an endpoint during the etching of a material within a recess such as a trench or a contact via. The method provides a clear and distinct inflection endpoint signal, even for areas of a substrate containing isolated features. The method includes etching the material in the recess and using thin film interferometric endpoint detection to detect an endpoint of the etch process, where the interferometric incident light beam wavelength is tailored to the material being etched; the spot size of the substrate illuminated by the light beam is sufficient to provide adequate signal intensity from the material being etched; and the refractive index of the material being etched is sufficiently different from the refractive index of other materials contributing to reflected light from the substrate, that the combination of the light beam wavelength, the spot size, and the difference in refractive index provides a clear and distinct endpoint signal.Type: ApplicationFiled: October 29, 2001Publication date: May 1, 2003Applicant: Applied Materials, Inc.Inventors: Wilfred Pau, Meihua Shen, Jeffrey D. Chinn
-
Patent number: 6551941Abstract: A method of forming a notch silicon-containing gate structure is disclosed. This method is particularly useful in forming a T-shaped silicon-containing gate structure. A silicon-containing gate layer is etched to a first desired depth using a plasma generated from a first source gas. During the etch, etch byproducts deposit on upper sidewalls of the silicon-containing gate layer which are exposed during etching, forming a first passivation layer which protects the upper silicon-containing gate layer sidewalls from etching during subsequent processing steps. A relatively high substrate bias power is used during this first etch step to ensure that the passivation layer adheres properly to the upper silicon-containing gate sidewalls.Type: GrantFiled: February 22, 2001Date of Patent: April 22, 2003Assignee: Applied Materials, Inc.Inventors: Chan-syun David Yang, Meihua Shen, Oranna Yauw, Jeffrey D. Chinn
-
Publication number: 20030071015Abstract: A two-step method of releasing microelectromechanical devices from a substrate is disclosed. The first step comprises isotropically etching a silicon oxide layer sandwiched between two silicon-containing layers with a gaseous hydrogen fluoride-water mixture, the overlying silicon layer to be separated from the underlying silicon layer or substrate for a time sufficient to form an opening but not to release the overlying layer, and the second step comprises adding a drying agent to substitute for moisture remaining in the opening and to dissolve away any residues in the opening that can cause stiction.Type: ApplicationFiled: October 8, 2002Publication date: April 17, 2003Applicant: APPLIED MATERIALS, INC.Inventors: Jeffrey D. Chinn, Sofiane Soukane
-
Publication number: 20030038110Abstract: A chemical-mechanical jet etching method rapidly removes large amounts of material in wafer thinning, or produces large-scale features on a silicon wafer, gallium arsenide substrate, or similar flat semiconductor workpiece, at etch rates in the range of 10-100 microns of workpiece thickness per minute. A nozzle or array of nozzles, optionally including a dual-orifice nozzle, delivers a high-pressure jet of machining etchant fluid to the surface of the workpiece. The machining etchant comprises a liquid or gas, carrying particulate material. The liquid may be a chemical etchant, or a solvent for a chemical etchant, if desired. The areas which are not to be etched may be shielded from the jet by a patterned mask, or the jet may be directed at areas from which material is to be removed, as in wafer thinning or direct writing, depending on the size of the desired feature or etched area.Type: ApplicationFiled: August 17, 2001Publication date: February 27, 2003Inventors: Robert Z. Bachrach, Jeffrey D. Chinn
-
Publication number: 20030029835Abstract: A two-step method of etching an organic coating layer, in particular, an organic antireflection coating (ARC) layer, is disclosed. During the main etch step, the organic coating layer is etched using a plasma generated from a first source gas which includes a fluorocarbon and a non-carbon-containing, halogen-comprising gas. Etching is performed using a first substrate bias power. During the overetch step, residual organic coating material remaining after the main etch step is removed by exposing the substrate to a plasma generated from a second source gas which includes a chlorine-containing gas and an oxygen-containing gas, and which does not include a polymer-forming gas. The overetch step is performed using a second substrate bias power which is less than the first substrate bias power.Type: ApplicationFiled: March 20, 2001Publication date: February 13, 2003Inventors: Oranna Yauw, Meihua Shen, Nicolas Gani, Jeffrey D. Chinn
-
Patent number: 6518190Abstract: A preferred embodiment of the plasma reactor of the present invention provides a chamber adapted to process a workpiece having at least one wall capable of allowing inductive power coupling into the reactor chamber. A source power antenna, capable of generating a processing plasma, confronts a portion of the at least one wall. A dry clean antenna is located adjacent the chamber beside a portion of the at least one wall not confronted by the source power antenna. During workpiece processing, the dry clean antenna preferably has essentially a floating potential. After workpiece processing has ceased, a dry clean plasma may be generated by inductive coupling using the dry clean antenna. Embodiments of the present invention allow dry clean plasma characteristics to be optimized to improve dry clean effectiveness. The source power antenna also may couple power to the dry clean plasma, preferably in parallel with the dry clean antenna.Type: GrantFiled: December 23, 1999Date of Patent: February 11, 2003Assignee: Applied Materials Inc.Inventors: Thorsten Lill, Jeffrey D. Chinn
-
Patent number: 6518192Abstract: A two-step etch method for etching a masked layer or layers that include fast and slow etching regions is described. Fast and slow etching regions may arise in a variety of devices, such as microelectrical mechanical system (“MEMS”) applications and mixed signal (i.e. analog and digital) integrated circuits, as well as other integrated circuits and devices. In one embodiment, a first etchant is used to etch through the layer in the fastest etching region, and then a second etchant is used to complete etching through the layer in the slowest etching region.Type: GrantFiled: December 7, 2001Date of Patent: February 11, 2003Assignee: Applied Materials Inc.Inventors: Anisul Khan, Ajay Kumar, Jeffrey D. Chinn, Dragan Podlesnik
-
Publication number: 20030003752Abstract: Processes for forming trenches within silicon substrates are described. According to an embodiment of the invention, a masked substrate is initially provided that comprises (a) a silicon substrate and (b) a patterned resist layer over the silicon substrate. The patterned resist layer has one or more apertures formed therein. Subsequently, a trench is formed in the substrate through the apertures in the resist layer by an inductive plasma-etching step, which is conducted using plasma source gases that comprise SF6, at least one fluorocarbon gas, and N2. If desired, Cl2 can also be provided in addition to the above source gases. The process of the present invention produces chamber deposits in low amounts, while providing high etching rates, high silicon:resist selectivities, and good trench sidewall profile control.Type: ApplicationFiled: June 27, 2001Publication date: January 2, 2003Inventors: Shashank Deshmukh, David Mui, Jeffrey D. Chinn, Dragan V. Podlesnik
-
Publication number: 20020164879Abstract: The invention includes methods of forming microstructure devices. In an exemplary method, a substrate is provided which includes a first material and a second material. At least one of the first and second materials is exposed to vapor-phase alkylsilane-containing molecules to form a coating over the at least one of the first and second materials.Type: ApplicationFiled: May 7, 2001Publication date: November 7, 2002Applicant: Applied Materials, Inc.Inventors: Toi Yue Becky Leung, Jeffrey D. Chinn
-
Publication number: 20020163051Abstract: Microstructure devices, methods of forming a microstructure device and a method of forming a MEMS device are described. According to one aspect, a microstructure device includes: a semiconductive substrate; a monolithic microstructure device feature coupled with the semiconductive substrate, and wherein at least a portion of the microstructure device feature is configured to move relative to the semiconductive substrate; and a conductive structure provided directly upon the microstructure device feature.Type: ApplicationFiled: May 7, 2001Publication date: November 7, 2002Applicant: Applied Materials, Inc.Inventors: Vidyut Gopal, Jeffrey D. Chinn
-
Publication number: 20020151183Abstract: A method of forming a notched silicon-containing gate structure is disclosed. This method is particularly useful in forming a T-shaped silicon-containing gate structure. A silicon-containing gate layer is etched to a first desired depth using a plasma generated from a first source gas. During the etch, etch byproducts deposit on upper sidewalls of the silicon-containing gate layer which are exposed during etching, forming a first passivation layer which protects the upper silicon-containing gate layer sidewalls from etching during subsequent processing steps. A relatively high substrate bias power is used during this first etch step to ensure that the passivation layer adheres properly to the upper silicon-containing gate sidewalls.Type: ApplicationFiled: February 22, 2001Publication date: October 17, 2002Inventors: Chan-syun David Yang, Meihua Shen, Oranna Yauw, Jeffrey D. Chinn
-
Publication number: 20020106845Abstract: A method for processing a substrate disposed in a substrate processing chamber to modify the contour of a trench formed on the substrate. The substrate processing chamber is the type that has a coil and a plasma generation system including a source power system operatively coupled to the coil and a bias power system operatively coupled to the substrate process chamber. The method includes transferring the substrate into the substrate process chamber. Thereafter, the substrate is exposed to a plasma formed from a first process gas consisting essentially of a sputtering agent by applying RF energy from the source power system to the coil. The plasma is biased toward the substrate by applying bias power to the substrate process chamber. Thereafter, the substrate is exposed to a plasma formed from a second process gas without applying bias power or applying minimal bias power to the substrate process chamber.Type: ApplicationFiled: November 29, 1999Publication date: August 8, 2002Inventors: JOHN CHAO, MOHIT JAIN, JEFFREY D. CHINN
-
Patent number: 6415198Abstract: A method of etching silicon using a chlorine and sulfur dioxide gas chemistry. An embodiment of the method is accomplished using a 20 to 300 sccm of chlorine and 2 to 100 sccm of sulfur dioxide, regulated to a total chamber pressure of 2-100 mTorr.Type: GrantFiled: June 25, 1999Date of Patent: July 2, 2002Assignee: Applied Materials, Inc.Inventors: Padmapani C. Nallan, Ajay Kumar, Jeffrey D. Chinn
-
Patent number: 6391788Abstract: A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.Type: GrantFiled: February 25, 2000Date of Patent: May 21, 2002Assignee: Applied Materials, Inc.Inventors: Anisul Khan, Ajay Kumar, Jeffrey D. Chinn, Dragan Podlesnik
-
Patent number: 6383941Abstract: The present disclosure relates to semiconductor processing, and to the plasma etching of organic layers, and in particular antireflective coating layers. We have discovered a particular combination of gases useful in producing chemically reactive plasma species, which provides unexpected control over etched feature critical dimension, etch profile, and uniformity of etch across a substrate surface, despite a difference in the spacing of etched features over the substrate surface. The combination of gases which produces chemically reactive plasma species consists essentially of CxHyFz, a bromine-comprising compound (which is typically HBr), and O2, where x ranges from 1 to 4, y ranges from 0 to 3, and z ranges from 1 to 10. Oxygen atoms may be substituted for hydrogen atoms in the CxHyFz compound to a limited extent Essentially inert gases which do not produce chemically reactive species may be added to the combination of etchant-species producing gases.Type: GrantFiled: July 6, 2000Date of Patent: May 7, 2002Assignee: Applied Materials, Inc.Inventors: Meihua Shen, Kenju Nishikido, Jeffrey D. Chinn, Dragan Podlesnik
-
Publication number: 20020052113Abstract: A two-step etch method for etching a masked layer or layers that include fast and slow etching regions is described. Fast and slow etching regions may arise in a variety of devices, such as microelectrical mechanical system (“MEMS”) applications and mixed signal (i.e. analog and digital) integrated circuits, as well as other integrated circuits and devices. In one embodiment, a first etchant is used to etch through the layer in the fastest etching region, and then a second etchant is used to complete etching through the layer in the slowest etching region.Type: ApplicationFiled: December 7, 2001Publication date: May 2, 2002Applicant: Applied Materials, Inc.Inventors: Anisul Khan, Ajay Kumar, Jeffrey D. Chinn, Dragan Podlesnik
-
Patent number: 6372151Abstract: The method of present invention etches a layer of polysilicon formed on a substrate disposed within a substrate processing chamber. The method flows an etchant gas including sulfur hexafluoride, an oxygen source and a nitrogen source into the processing chamber and ignites a plasma from the etchant gas to etch the polysilicon formed over the substrate. In a preferred embodiment, the etchant gas consists essentially of SF6, molecular oxygen (O2) and molecular nitrogen (N2). In a more preferred embodiment the etchant gas includes a volume ratio of molecular oxygen to the sulfur hexafluoride of between 0.5:1 and 1:1 inclusive and a volume ratio of the sulfur hexafluoride to molecular nitrogen of between 1:1 and 4:1 inclusive. In an even more preferred embodiment, the volume ratio of O2 to sulfur hexafluoride is between 0.5:1 and 1:1 inclusive and the volume ratio of sulfur hexafluoride to N2 is between 1.5:1 and 2:1 inclusive.Type: GrantFiled: July 27, 1999Date of Patent: April 16, 2002Assignee: Applied Materials, Inc.Inventors: Taeho Shin, Nam-Hun Kim, Jeffrey D. Chinn