Patents by Inventor Jeffrey D. Punzalan

Jeffrey D. Punzalan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8203220
    Abstract: A method for manufacturing an integrated circuit package system includes: forming a first device unit, having first external interconnects arranged along a perimeter of the first device unit, and a second device unit, having second external interconnects arranged along a perimeter of the second device unit, in an array configuration; mounting an integrated circuit die over the first device unit; connecting the integrated circuit die and the first external interconnects; encapsulating with an encapsulation covering the integrated circuit die, the first device unit, and the second device unit with both the first external interconnects and the second external interconnects partially exposed; and forming a partial encapsulation cut in the encapsulation electrically isolating the first external interconnects and the second electrical interconnects.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: June 19, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Lionel Chien Hui Tay, Zigmund Ramirez Camacho, Jeffrey D. Punzalan, Arnel Trasporto
  • Patent number: 8148825
    Abstract: An integrated circuit package system includes: providing a lead terminal; forming a dummy lead near the lead terminal; positioning a base integrated circuit adjacent the lead terminal and the dummy lead; connecting a die connector to the base integrated circuit and the dummy lead; mounting a stackable integrated circuit over the base integrated circuit; and connecting another of the die connector to the stackable integrated circuit and the dummy lead.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: April 3, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Jairus Legaspi Pisigan, Jeffrey D. Punzalan
  • Patent number: 8129827
    Abstract: An integrated circuit package system includes: forming an external interconnect; connecting an integrated circuit die and the external interconnect; forming a package encapsulation, having a recess, covering the integrated circuit die with a portion of the external interconnect exposed by the recess; and connecting an integrated circuit device and the external interconnect in the recess.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: March 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Jeffrey D. Punzalan, Jairus Legaspi Pisigan, Abelardo Jr Hadap Advincula
  • Patent number: 8120156
    Abstract: The present invention provides an integrated circuit package system with die on base package comprising forming a base package comprising, forming a substrate, mounting a first integrated circuit on the substrate, encapsulating the integrated circuit and the substrate with a molding compound, and testing the base package, attaching a bare die to the base package, connecting electrically the bare die to the substrate and encapsulating the bare die and the base package.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: February 21, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • Patent number: 8120150
    Abstract: An integrated circuit package system includes: forming a die-attach paddle, a terminal pad, and an external interconnect with the external interconnect below the terminal pad; connecting an integrated circuit die with the terminal pad and the external interconnect; and forming an encapsulation, having a first side and a second side at an opposing side to the first side, surrounding the integrated circuit die with the terminal pad exposed at the first side and the external interconnect extending below the second side.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: February 21, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Guruprasad Badakere Govindaiah, Zigmund Ramirez Camacho, Jeffrey D. Punzalan, Henry Descalzo Bathan, Lionel Chien Hui Tay
  • Patent number: 8120149
    Abstract: An integrated circuit package system is provided forming a lead finger from a padless lead frame, forming a lead tip hole in the lead finger, mounting an integrated circuit die having a solder bump on the lead finger, and reflowing the solder bump on the lead tip hole of the lead finger.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: February 21, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • Publication number: 20110298108
    Abstract: A non-leaded integrated circuit package system includes: a die paddle of a lead frame; a dual row of terminals including an outer terminal and an inner terminal; and an inner terminal and an adjacent inner terminal to form a fused lead.
    Type: Application
    Filed: August 22, 2011
    Publication date: December 8, 2011
    Inventors: Jeffrey D. Punzalan, Byung Tai Do, Henry D. Bathan, Zigmund Ramirez Camacho
  • Publication number: 20110284842
    Abstract: An integrated circuit package system with laminate base includes: a base package including: a laminate substrate strip, an integrated circuit on the laminate substrate strip, a molded cover over the integrated circuit and the laminate substrate strip, and a strip test of the base package; a bare die on the base package; the bare die electrically connected to the laminate substrate strip; and the bare die and the base package encapsulated.
    Type: Application
    Filed: August 2, 2011
    Publication date: November 24, 2011
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • Patent number: 8062934
    Abstract: An integrated circuit package system comprising: forming leads adjacent a die paddle having a die pad extension; forming a region having one of the leads depopulated for the die pad extension; and connecting an integrated circuit die to the die pad extension.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: November 22, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Jeffrey D. Punzalan, Henry Descalzo Bathan, Zigmund Ramirez Camacho
  • Patent number: 8039947
    Abstract: An integrated circuit package system is provided including forming a first inner lead having a first inner bottom side and a first outer lead, forming a first side lock of the first inner lead above the first inner bottom side, connecting an integrated circuit die with the first inner lead and the first outer lead, and encapsulating the integrated circuit die and the first side lock.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: October 18, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Jeffrey D. Punzalan, Henry Descalzo Bathan, Zigmund Ramirez Camacho
  • Patent number: 8035204
    Abstract: A method for fabricating large die package structures is provided wherein at least portions of the leadtips of at least a plurality of leadfingers of a leadframe are electrically insulated. A die is positioned on the electrically insulated leadtips. The die is electrically connected to at least a plurality of the leadfingers.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: October 11, 2011
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Jeffrey D. Punzalan, Jose Alvin Caparas, Jae Hun Ku
  • Patent number: 8022514
    Abstract: An integrated circuit package system including forming a leadframe having a lead with a leadfinger support of a predetermined height, and attaching an integrated circuit die with an electrical interconnect at a predetermined collapse height determined by the predetermined height of the leadfinger support.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: September 20, 2011
    Assignee: STATS ChipPAC Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Arnel Senosa Trasporto, Jeffrey D. Punzalan
  • Publication number: 20110204501
    Abstract: An integrated circuit packaging system includes: a plurality of leads with a predetermined thickness and a predetermined interval gap between each of the plurality of leads; each one of the plurality of leads includes first terminal ends disposed adjacent an integrated circuit and second terminal ends disposed along a periphery of a package; and a lead-to-lead gap formed between the second terminal ends of alternating leads in excess of the predetermined interval gap.
    Type: Application
    Filed: May 4, 2011
    Publication date: August 25, 2011
    Inventors: Jeffrey D. Punzalan, Henry D. Bathan, Il Kwon Shim, Keng Kiat Lau
  • Patent number: 8003443
    Abstract: A non-leaded integrated circuit package system is provided providing a die paddle of a lead frame, forming a dual row of terminals including an outer terminal and an inner terminal, and selectively fusing an inner terminal and an adjacent inner terminal to form a fused lead.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: August 23, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Jeffrey D. Punzalan, Byung Tai Do, Henry D. Bathan, Zigmund Ramirez Camacho
  • Patent number: 7993939
    Abstract: An integrated circuit package system with laminate base is provided including forming a base package including, forming a laminate substrate strip, mounting an integrated circuit on the laminate substrate strip, forming a molded cover over the integrated circuit and the laminate substrate strip, and performing a strip test of the base package; attaching a bare die to the base package; connecting electrically the bare die to the laminate substrate strip; and encapsulating the bare die and the base package.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: August 9, 2011
    Assignee: STATS Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • Patent number: 7977579
    Abstract: An integrated circuit package system includes forming a multi-tier substrate, and attaching a plurality of integrated circuits on the multi-tier substrate.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: July 12, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Henry D. Bathan, Zigmund Ramirez Camacho, Jr., Arnel Trasporto, Jeffrey D. Punzalan
  • Patent number: 7947534
    Abstract: An integrated circuit package system is provided including: forming a plurality of leads with a predetermined thickness and a predetermined interval gap between each of the plurality of leads; configuring each one of the plurality of leads to include first terminal ends disposed adjacent an integrated circuit and second terminal ends disposed along a periphery of a package; and forming the second terminal ends of alternating leads disposed along the periphery of the package to form an etched lead-to-lead gap in excess of the predetermined interval gap.
    Type: Grant
    Filed: February 4, 2006
    Date of Patent: May 24, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Jeffrey D. Punzalan, Henry D. Bathan, Il Kwon Shim, Keng Kiat Lau
  • Publication number: 20110101524
    Abstract: A semiconductor device includes a semiconductor die having contact pads disposed over a surface of the semiconductor die, a die attach adhesive layer disposed under the semiconductor die, and an encapsulant material disposed around and over the semiconductor die. The semiconductor device further includes bumps disposed in the encapsulant material around a perimeter of the semiconductor die. The bumps are partially enclosed by the encapsulant material. The semiconductor device further comprises first vias disposed in the encapsulant. The first vias expose surfaces of the contact pads. The semiconductor device further includes a first redistribution layer (RDL) disposed over the encapsulant and in the first vias, and a second RDL disposed under the encapsulant material and the die attach adhesive layer. The first RDL electrically connects each contact pad of the semiconductor die to one of the bumps, and the second RDL is electrically connected to one of the bumps.
    Type: Application
    Filed: January 6, 2011
    Publication date: May 5, 2011
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Zigmund R. Camacho, Lionel Chien Hui Tay, Henry D. Bathan, Jeffrey D. Punzalan
  • Patent number: 7936053
    Abstract: An integrated circuit package system includes forming lead structures including a dummy tie bar having an intersection with an outer edge of the integrated circuit package system, and connecting an integrated circuit die to the lead structures.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: May 3, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Jeffrey D. Punzalan, Henry D. Bathan, Il Kwon Shim, Zigmund Ramirez Camacho
  • Patent number: 7928540
    Abstract: An integrated circuit package system is provided including forming an external interconnect having a lead body and a lead tip, forming a lead protrusion in the lead tip, connecting a device and the external interconnect, and encapsulating the device and the external interconnect.
    Type: Grant
    Filed: November 10, 2006
    Date of Patent: April 19, 2011
    Assignee: STATS ChipPAC Ltd.
    Inventors: Il Kwon Shim, Antonio B. Dimaano, Jr., Henry D. Bathan, Jeffrey D. Punzalan