Patents by Inventor Jeffrey D. Punzalan

Jeffrey D. Punzalan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7443015
    Abstract: An integrated circuit package system includes an integrated circuit package having a downset terminal lead, a planar recessed lead surface of the downset terminal lead, and an attached integrated circuit over the planar recessed lead surface.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: October 28, 2008
    Assignee: Stats Chippac Ltd.
    Inventors: Jeffrey D. Punzalan, Sheila Marie L. Alvarez, Jose Alvin Caparas, Robinson Quiazon
  • Publication number: 20080251901
    Abstract: A stacked integrated circuit package system is provided providing a lead frame having a die paddle, attaching a first integrated circuit on the die paddle of the lead frame, connecting first electrical interconnects between the first integrated circuit and the lead frame, encapsulating the first integrated circuit and the first electrical interconnects with the lead frame directly on a bottom mold and clamped by a top mold, attaching a second integrated circuit on the die paddle of the first integrated circuit, connecting second electrical interconnects between the second integrated circuit and the lead frame, and encapsulating the second integrated circuit and the second electrical interconnects.
    Type: Application
    Filed: April 28, 2008
    Publication date: October 16, 2008
    Inventors: Zigmund Ramirez Camacho, Wong Sze Min, Arnel Trasporto, Jeffrey D. Punzalan
  • Publication number: 20080237816
    Abstract: An integrated circuit package system is provided including forming a lead frame includes forming a mold gate, providing a first surface, and providing a second surface opposite the first surface; and forming angled gate sides facing each other in the mold gate between the first surface and the second surface.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Henry Descalzo Bathan, Jeffrey D. Punzalan, Abelardo Hadap Advincula, Jose Alvin Caparas
  • Patent number: 7420265
    Abstract: An integrated circuit package system including an integrated circuit die, a leadframe and an integrated circuit support. The integrated circuit support between the integrated circuit die and the leadframe with the electrical interconnects connected to the leadframe.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: September 2, 2008
    Assignee: Stats Chippac Ltd.
    Inventors: Henry D. Bathan, Il Kwon Shim, Jeffrey D. Punzalan, Zigmund Ramirez Camacho
  • Patent number: 7413933
    Abstract: A semiconductor including a leadframe having a die attach paddle and a number of leads is provided. The die attach paddle has a recess to provide a number of mold dams around the periphery of the die attach paddle. An integrated circuit is positioned in the recess. Electrical connections between the integrated circuit and the number of leads are made, and an encapsulant is formed over the integrated circuit and around the number of mold dams.
    Type: Grant
    Filed: April 9, 2007
    Date of Patent: August 19, 2008
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Jeffrey D. Punzalan, Jae Hun Ku, Byung Joon Han
  • Publication number: 20080185693
    Abstract: An integrated circuit package system is provided including forming a paddle, an outer lead, and an inner lead between the paddle and the outer lead; forming a non-vertical paddle edge of the paddle and a non-vertical lead edge of the inner lead facing the non-vertical paddle edge; and encapsulating an integrated circuit die over the paddle.
    Type: Application
    Filed: February 2, 2007
    Publication date: August 7, 2008
    Inventors: Jeffrey D. Punzalan, Henry Descalzo Bathan, Zigmund Ramirez Camacho, Arnel Trasporto
  • Patent number: 7400049
    Abstract: An integrated circuit package system is provided forming an external interconnect from a padless lead frame, encapsulating a heat sink and the external interconnect, mounting an integrated circuit die on the heat sink, and encapsulating the integrated circuit die, the heat sink, and the external interconnect.
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: July 15, 2008
    Assignee: Stats Chippac Ltd.
    Inventors: Il Kwon Shim, Henry D. Bathan, Zigmund Ramirez Camacho, Jeffrey D. Punzalan
  • Publication number: 20080142934
    Abstract: An integrated circuit package system includes an elevated edge leadframe array, isolating leadframes of the elevated edge leadframe array, validating integrated circuit die attached to the leadframes, and forming integrated circuit packages including the integrated circuit die.
    Type: Application
    Filed: December 13, 2006
    Publication date: June 19, 2008
    Applicant: STATS CHIPPAC LTD.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Jose Alvin Caparas, Jeffrey D. Punzalan
  • Publication number: 20080111217
    Abstract: An integrated circuit package system is provided including forming a paddle, forming a ring with a recess in the paddle, mounting a device in the recess, forming a slot in the ring, and mounting a heat sink in the slot over the device.
    Type: Application
    Filed: November 9, 2006
    Publication date: May 15, 2008
    Applicant: STATS ChipPAC Ltd.
    Inventors: Antonio B. Dimaano, Il Kwon Shim, Henry D. Bathan, Jeffrey D. Punzalan
  • Publication number: 20080111215
    Abstract: An integrated circuit package system is provided including forming an external interconnect having a lead body and a lead tip, forming a lead protrusion in the lead tip, connecting a device and the external interconnect, and encapsulating the device and the external interconnect.
    Type: Application
    Filed: November 10, 2006
    Publication date: May 15, 2008
    Applicant: STATS ChipPAC Ltd.
    Inventors: Il Kwon Shim, Antonio B. Dimaano, Henry D. Bathan, Jeffrey D. Punzalan
  • Patent number: 7365417
    Abstract: An integrated circuit package system is provided attaching a film to a die paddle, applying an adhesive to the film, and attaching an integrated circuit die over the adhesive and the film to the die paddle.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: April 29, 2008
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • Patent number: 7339258
    Abstract: A semiconductor package is provided. A leadframe including a die attach paddle, a number of inner leads, and a number of outer leads, and a number of extended lead tips on the number of outer leads. The inner edges of the number of extended lead tips are in substantial alignment with the inner edges of the number of inner leads. A die is attached to the die attach paddle. A number of bonding wires is used to connect the die to the number of inner leads and the extended lead tips on the number of outer leads, and an encapsulant is formed over the leadframe and the die.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: March 4, 2008
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Jeffrey D. Punzalan, Jose Alvin Caparas, Jae Hun Ku
  • Publication number: 20080017960
    Abstract: An integrated circuit package system with laminate base is provided including forming a base package including, forming a laminate substrate strip, mounting an integrated circuit on the laminate substrate strip, forming a molded cover over the integrated circuit and the laminate substrate strip, and performing a strip test of the base package; attaching a bare die to the base package; connecting electrically the bare die to the laminate substrate strip; and encapsulating the bare die and the base package.
    Type: Application
    Filed: July 21, 2006
    Publication date: January 24, 2008
    Applicant: STATS CHIPPAC LTD.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • Publication number: 20080012100
    Abstract: An integrated circuit package system is provided including forming a lead frame including forming an inner lead having a planar surface, the inner lead extending inwardly from the lead frame and forming a stiffening structure integral with the lead frame for maintaining the planar surface; encapsulating the inner lead with an electrical connection to an integrated circuit die and with a first inner lead body of the inner lead exposed; and singulating the inner lead from the lead frame.
    Type: Application
    Filed: February 2, 2007
    Publication date: January 17, 2008
    Inventors: Jeffrey D. Punzalan, Henry D. Bathan, Il Kwon Shim, Zigmund Ramirez Camacho
  • Publication number: 20080006926
    Abstract: An integrated circuit package system is provided including forming a mounting structure having an external interconnect, a paddle, and a tie bar; mounting an integrated circuit die on the paddle; soldering a stiffener structure; having an opening; on the mounting structure; connecting the stiffener structure to a ground; and molding the integrated circuit die and partially the stiffener structure through the opening.
    Type: Application
    Filed: July 10, 2006
    Publication date: January 10, 2008
    Applicant: STATS CHIPPAC LTD.
    Inventors: Henry D. Bathan, Antonio B. Dimaano, Jeffrey D. Punzalan, Zigmund Ramirez Camacho
  • Publication number: 20080006929
    Abstract: An integrated circuit package system comprising: forming leads adjacent a die paddle having a die pad extension; forming a region having one of the leads depopulated for the die pad extension; and connecting an integrated circuit die to the die pad extension.
    Type: Application
    Filed: June 21, 2007
    Publication date: January 10, 2008
    Inventors: Jeffrey D. Punzalan, Henry Descalzo Bathan, Zigmund Ramirez Camacho
  • Publication number: 20070267731
    Abstract: An integrated circuit package system is provided including forming a first inner lead having a first inner bottom side and a first outer lead, forming a first side lock of the first inner lead above the first inner bottom side, connecting an integrated circuit die with the first inner lead and the first outer lead, and encapsulating the integrated circuit die and the first side lock.
    Type: Application
    Filed: May 16, 2007
    Publication date: November 22, 2007
    Inventors: Jeffrey D. Punzalan, Henry Descalzo Bathan, Zigmund Ramirez Camacho
  • Patent number: 7298026
    Abstract: A method for fabricating a large die package with a leadframe having leads and a paddle is provided. An interposer is attached onto the leadframe with the interposer extending over at least a portion of the paddle and at least a portion of the leads of the lead-frame. The interposer is insulated from the leads. A die is attached to the interposer.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: November 20, 2007
    Assignee: Stats Chippac Ltd.
    Inventors: Il Kwon Shim, Jeffrey D. Punzalan, Keng Kiat Lau
  • Patent number: 7274089
    Abstract: An integrated circuit package system including an integrated circuit die and a lead frame with a trenched die pad. The integrated circuit die is mounted to the trenched die pad.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: September 25, 2007
    Assignee: Stats Chippac Ltd.
    Inventors: Jeffrey D. Punzalan, Il Kwon Shim, Zigmund Ramirez Camacho, Henry D. Bathan
  • Publication number: 20070170559
    Abstract: An integrated circuit package system is provided forming a lead finger from a padless lead frame, forming a lead tip hole in the lead finger, mounting an integrated circuit die having a solder bump on the lead finger, and reflowing the solder bump on the lead tip hole of the lead finger.
    Type: Application
    Filed: January 24, 2006
    Publication date: July 26, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan