Patents by Inventor Jen-Hao Yeh
Jen-Hao Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170271511Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.Type: ApplicationFiled: June 5, 2017Publication date: September 21, 2017Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun Lin Tsai
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Publication number: 20170257074Abstract: A dissipative device has a planar configuration with one or more resistor elements formed on an insulating substrate. Conductors are formed on the insulating substrate and are coupled to the resistor element(s) to transmit signals to/from the resistor element(s). The geometry of and materials for the dissipative device allow the conductors to act as heat sinks, which conduct heat generated in the resistor element(s) to the substrate (and on to a coupled housing) and cool hot electrons generated by the resistor element(s) via electron-phonon coupling. The dissipative device can be used in cooling a signal to a qubit, a cavity system of a quantum superconducting qubit, or any other cryogenic device sensitive to thermal noise.Type: ApplicationFiled: March 2, 2017Publication date: September 7, 2017Applicants: University of Maryland, College Park, The United States of America as represented by the Director, National Security AgencyInventors: Jen-Hao Yeh, Benjamin S. Palmer, Frederick C. Wellstood, Jay LeFebvre
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Patent number: 9742434Abstract: Data compression/decompression methods and data compressor/de-compressor are provided. The data compression method includes the steps of scaling an input signal to generate a scaled signal; transmitting the scaled signal to a differentiator and an assembler; differentiating the scaled signal and a prior signal to generate a differentiation signal detecting zero bits of the differentiation signal to generate a zero range control signal and a zero range control word; refining the differentiation signal according to the zero range control signal to generate a refined signal; and determining to combine the zero range control word with the scaled signal or combine the zero range control word with the refined signal according to the zero range control word to generate a compressed signal.Type: GrantFiled: December 23, 2016Date of Patent: August 22, 2017Assignee: MEDIATEK INC.Inventors: Chih-Chuan Liang, Jen-Hao Yeh, Ming-Yang Chao, Yao-Jen Liu
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Patent number: 9673323Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.Type: GrantFiled: January 22, 2016Date of Patent: June 6, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun-Lin Tsai
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Patent number: 9660108Abstract: A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region.Type: GrantFiled: November 4, 2015Date of Patent: May 23, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker-Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun Lin Tsai
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Publication number: 20160308036Abstract: A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), and more particularly an insulated gate bipolar junction transistor (IGBT), is disclosed. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.Type: ApplicationFiled: June 24, 2016Publication date: October 20, 2016Inventors: Ker-Hsiao Huo, Fu-Chih Yang, Jen-Hao Yeh, Chun Lin Tsai, Chih-Chang Cheng, Ru-Yi Su
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Patent number: 9424161Abstract: A trace capture device includes a processing system, a trace capture control unit and a bus unit. The processing system includes at least one function block arranged to generate first data, second data, and correlation information corresponding to the first data. The trace capture control unit is arranged to receive the first data and correlation information corresponding to the first data from the processing system, and generate third data according to the first data and the correlation information. The bus unit is coupled to the processing system, the trace capture control unit and a data link interface. The bus unit is arranged to use the data link interface to transmit information derived from the second data in a first mode, and reuse the first data link interface to transmit information derived from the third data in a second mode.Type: GrantFiled: June 8, 2014Date of Patent: August 23, 2016Assignee: MEDIATEK INC.Inventors: Jen-Hao Yeh, Chih-Chuan Liang, Ming-Yang Chao
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Patent number: 9379188Abstract: A method of making a high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), is disclosed. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.Type: GrantFiled: December 14, 2015Date of Patent: June 28, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ker-Hsiao Huo, Chih-Chang Cheng, Fu-Chih Yang, Jen-Hao Yeh, Chun Lin Tsai, Ru-Yi Su
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Publication number: 20160155841Abstract: An embodiment of a structure provides an enhanced performing high voltage device, configured as a lateral diffused MOS (HV LDMOS) formed in a tri-well structure (a small n-well in an extended p-type well inside an n-type well) within the substrate with an anti-punch through layer and a buried layer below the n-type well, which reduces substrate leakage current to almost zero. The drain region is separated into two regions, one within the small n-well and one contacting the outer n-type well such that the substrate is available for electric potential lines during when a high drain voltage is applied.Type: ApplicationFiled: February 8, 2016Publication date: June 2, 2016Inventors: Ker Hsiao Huo, Chih-Chang Cheng, Ru-Yi Su, Jen-Hao Yeh, Fu-Chih Yang, Chun Lin Tsai
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Publication number: 20160141418Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.Type: ApplicationFiled: January 22, 2016Publication date: May 19, 2016Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun-Lin Tsai
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Publication number: 20160111498Abstract: A method of making a high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), is disclosed. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.Type: ApplicationFiled: December 14, 2015Publication date: April 21, 2016Inventors: Ker-Hsiao Huo, Chih-Chang Cheng, Fu-Chih Yang, Jen-Hao Yeh, Chun Lin Tsai
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Publication number: 20160056303Abstract: A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region.Type: ApplicationFiled: November 4, 2015Publication date: February 25, 2016Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker-Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun Lin Tsai
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Patent number: 9257979Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.Type: GrantFiled: January 28, 2014Date of Patent: February 9, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun-Lin Tsai
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Patent number: 9257533Abstract: A method for fabricating a high voltage semiconductor transistor includes growing a first well region over a substrate having a first conductivity type, the first well region having a second type of conductivity. First, second and third portions of a second well region having the first type of conductivity are doped into the first well region. A first insulating layer is grown in and over the first well portion within the second well region. A second insulating layer is grown on the substrate over the third portion of the second well region. An anti-punch through region is doped into the first well region. A gate structure is formed on the substrate. A source region is formed in the first portion of the second well region on an opposite side of the gate structure from the first insulating layer. A drain region is formed in the first well region.Type: GrantFiled: November 5, 2014Date of Patent: February 9, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ker Hsiao Huo, Chih-Chang Cheng, Ru-Yi Su, Jen-Hao Yeh, Fu-Chih Yang, Chun Lin Tsai
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Patent number: 9214547Abstract: A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.Type: GrantFiled: October 11, 2013Date of Patent: December 15, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ker Hsiao Huo, Chih-Chang Cheng, Ru-Yi Su, Jen-Hao Yeh, Fu-Chih Yang, Chun Lin Tsai
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Publication number: 20150355991Abstract: A trace capture device includes a processing system, a trace capture control unit and a bus unit. The processing system includes at least one function block arranged to generate first data, second data, and correlation information corresponding to the first data. The trace capture control unit is arranged to receive the first data and correlation information corresponding to the first data from the processing system, and generate third data according to the first data and the correlation information. The bus unit is coupled to the processing system, the trace capture control unit and a data link interface. The bus unit is arranged to use the data link interface to transmit information derived from the second data in a first mode, and reuse the first data link interface to transmit information derived from the third data in a second mode.Type: ApplicationFiled: June 8, 2014Publication date: December 10, 2015Inventors: Jen-Hao Yeh, Chih-Chuan Liang, Ming-Yang Chao
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Patent number: 9190535Abstract: A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region.Type: GrantFiled: April 30, 2014Date of Patent: November 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun-Lin Tsai
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Patent number: 9093494Abstract: A guard structure for a semiconductor structure is provided. The guard structure includes a first guard ring, a second guard ring and a third guard ring. The first guard ring has a first conductivity type. The second guard ring has a second conductivity type, and surrounds the first guard ring. The third guard ring has the first conductivity type, and surrounds the second guard ring, wherein the first, the second and the third guard rings are grounded. A method of forming a guard layout pattern for a semiconductor layout pattern is also provided.Type: GrantFiled: February 28, 2013Date of Patent: July 28, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jaw-Juinn Horng, Jen-Hao Yeh, Fu-Chih Yang, Chung-Hui Chen
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Publication number: 20150072496Abstract: A method for fabricating a high voltage semiconductor transistor includes growing a first well region over a substrate having a first conductivity type, the first well region having a second type of conductivity. First, second and third portions of a second well region having the first type of conductivity are doped into the first well region. A first insulating layer is grown in and over the first well portion within the second well region. A second insulating layer is grown on the substrate over the third portion of the second well region. An anti-punch through region is doped into the first well region. A gate structure is formed on the substrate. A source region is formed in the first portion of the second well region on an opposite side of the gate structure from the first insulating layer. A drain region is formed in the first well region.Type: ApplicationFiled: November 5, 2014Publication date: March 12, 2015Inventors: Ker Hsiao HUO, Chih-Chang CHENG, Ru-Yi SU, Jen-Hao YEH, Fu-Chih YANG, Chun Lin TSAI
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Patent number: 8969913Abstract: A high voltage laterally diffused metal-oxide-semiconductor (HV LDMOS) device, particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate having at least one highly doped buried portion, a first doped well grown over the substrate, a gate structure formed on the first well, a source and a drain formed on either side of the gate structure, and a second doped well having a U-shaped cross section formed in the first well. A portion of the drain is formed over the first well outside of the second well.Type: GrantFiled: November 9, 2012Date of Patent: March 3, 2015Assignee: Taiwan Semiconductor Maufacturing Company, Ltd.Inventors: Ker Hsiao Huo, Chih-Chang Cheng, Ru-Yi Su, Jen-Hao Yeh, Fu-Chih Yang, Chun Lin Tsai