Abstract: Various methods are disclosed herein for reducing (or eliminating) printability of mask defects during lithography processes. An exemplary method includes performing a first lithography exposing process and a second lithography exposing process using a mask to respectively image a first set of polygons oriented substantially along a first direction and a second set of polygons oriented substantially along a second direction on a target. During the first lithography exposing process, a phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the first direction and a third direction that is different than the first direction. During the second lithography exposing process, the phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the second direction and a fourth direction that is different than the third direction.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. An inverse mask is provided. A sacrificial layer is deposited over a substrate. A patterned photoresist layer is formed over the sacrificial layer using the inverse mask. The sacrificial layer is then etched through the patterned photoresist layer to form a patterned sacrificial layer. A hard mask layer is deposited over the patterned sacrificial layer. The patterned sacrificial layer is then removed to form a second pattern on the hard mask layer.

Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a porous pellicle frame, a mask with a patterned surface, a first thermal conductive adhesive layer that secures the pellicle membrane to the porous pellicle frame, and a second thermal conductive adhesive layer that secures the porous pellicle frame to the mask.

Abstract: The present disclosure provides an embodiment of a reflective mask that includes a substrate; a reflective multilayer disposed on the substrate; an anti-oxidation barrier layer disposed on the reflective multilayer and the anti-oxidation barrier layer is in amorphous structure with an average interatomic distance less than an oxygen diameter; and an absorber layer disposed on the anti-oxidation barrier layer and patterned according to an integrated circuit layout.

Abstract: The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism.

Abstract: A lithography system includes a load lock chamber comprising an opening configured to receive a mask, an exposure module configured to expose a semiconductor wafer to a light source through use of the mask, and a cleaning module embedded inside the lithography tool, the cleaning module being configured to clean carbon particles from the mask.

Abstract: The present disclosure provides a method in accordance with some embodiments. A wafer is grinded from a back side. The wafer is inserted into an opening defined by a frame holder. The frame holder is attached to a carrier through a temporary layer. A front side of the wafer is attached to the temporary layer. Thereafter, the wafer is etched from the back side until the wafer reaches a predetermined thickness. Thereafter, the frame holder and the wafer therein are separated from the temporary layer and the carrier.

Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane with a thermal conductive surface; a porous pellicle frame; and a thermal conductive adhesive layer that secures the pellicle membrane to the porous pellicle frame. The porous pellicle frame includes a plurality of pore channels continuously extending from an exterior surface of the porous pellicle frame to an interior surface of the porous pellicle frame.

Abstract: Lithography methods and corresponding lithography apparatuses are disclosed herein for improving throughput of lithography exposure processes. An exemplary lithography method includes generating a plurality of target material droplets and generating radiation from the plurality of target material droplets based on a dose margin to expose a wafer. The dose margin indicates how many of the plurality of target material droplets are reserved for dose control. In some implementations, the plurality of target material droplets are grouped into a plurality of bursts, and the lithography method further includes performing an inter-compensation operation that designates an excitation state of target material droplets in one of the plurality of bursts to compensate for an energy characteristic of another one of the plurality of bursts.

Abstract: The present disclosure provides a method in accordance with some embodiments. A wafer is grinded from a back side. The wafer is inserted into an opening defined by a frame holder. The frame holder is attached to a carrier through a temporary layer. A front side of the wafer is attached to the temporary layer. Thereafter, the wafer is etched from the back side until the wafer reaches a predetermined thickness. Thereafter, the frame holder and the wafer therein are separated from the temporary layer and the carrier.

Abstract: Disclosed is an apparatus for lithography patterning. The apparatus includes a substrate stage configured to hold a substrate coated with a deposition enhancement layer (DEL), a radiation source for generating a patterned radiation towards a surface of the DEL, and a supply pipe for flowing an organic gas near the surface of the DEL, wherein elements of the organic gas polymerize upon the patterned radiation, thereby forming a resist pattern over the DEL.

Abstract: The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism.

Abstract: A lithography system includes a load lock chamber comprising an opening configured to receive a mask, an exposure module configured to expose a semiconductor wafer to a light source through use of the mask, and a cleaning module embedded inside the lithography tool, the cleaning module being configured to clean carbon particles from the mask.

Abstract: Systems and methods that include providing for measuring a first topographical height of a substrate at a first coordinate on the substrate and measuring a second topographical height of the substrate at a second coordinate on the substrate are provided. The measured first and second topographical heights may be provided as a wafer map. An exposure process is then performed on the substrate using the wafer map. The exposure process can include using a first focal point when exposing the first coordinate on the substrate and using a second focal plane when exposing the second coordinate on the substrate. The first focal point is determined using the first topographical height and the second focal point is determined using the second topographical height.

Abstract: Systems and methods that include providing for measuring a first topographical height of a substrate at a first coordinate on the substrate and measuring a second topographical height of the substrate at a second coordinate on the substrate are provided. The measured first and second topographical heights may be provided as a wafer map. An exposure process is then performed on the substrate using the wafer map. The exposure process can include using a first focal point when exposing the first coordinate on the substrate and using a second focal plane when exposing the second coordinate on the substrate. The first focal point is determined using the first topographical height and the second focal point is determined using the second topographical height.

Abstract: A method for fabricating a pellicle for EUV lithography processes includes placing a hard mask in contact with a surface of a substrate. In some embodiments, the hard mask is configured to pattern the surface of the substrate to include a first region and a second region surrounding the first region. By way of example, while the mask in positioned in contact with the substrate, an etch process of the substrate is performed to etch the first and second regions into the substrate. Thereafter, an excess substrate region is removed so as to separate the etched first region from the excess substrate region. In various embodiments, the etched and separated first region serves as a pellicle for an extreme ultraviolet (EUV) lithography process.

Abstract: A method includes patterning a resist layer formed over a substrate, resulting in a resist pattern; and transferring the resist pattern to an anti-reflection coating (ARC) layer formed under the resist layer and over the substrate, resulting in a patterned ARC layer. The method further includes treating the patterned ARC layer with an ion beam, resulting in a treated patterned ARC layer, wherein the ion beam is generated with a first gas and is directed towards the patterned ARC layer at a tilt angle at least 10 degrees. The method further includes etching the substrate with the treated patterned ARC layer as an etch mask.

Abstract: Lithography methods and corresponding lithography apparatuses are disclosed herein for improving throughput of lithography exposure processes. An exemplary lithography method includes generating a plurality of target material droplets and generating radiation from the plurality of target material droplets based on a dose margin to expose a wafer. The dose margin indicates how many of the plurality of target material droplets are reserved for dose control. In some implementations, the plurality of target material droplets are grouped into a plurality of bursts, and the lithography method further includes performing an inter-compensation operation that designates an excitation state of target material droplets in one of the plurality of bursts to compensate for an energy characteristic of another one of the plurality of bursts.

Abstract: A lithography system includes a radiation source configured to generate an extreme ultraviolet (EUV) light. The lithography system includes a mask that defines one or more features of an integrated circuit (IC). The lithography system includes an illuminator configured to direct the EUV light onto the mask. The mask diffracts the EUV light into a 0-th order ray and a plurality of higher order rays. The lithography system includes a wafer stage configured to secure a wafer that is to be patterned according to the one or more features defined by the mask. The lithography system includes a pupil phase modulator positioned in a pupil plane that is located between the mask and the wafer stage. The pupil phase modulator is configured to change a phase of the 0-th order ray.

Abstract: The present disclosure provides a photolithography mask. The photolithography mask includes a substrate that contains a low thermal expansion material (LTEM). A multilayer (ML) structure is disposed over the substrate. The ML structure is configured to reflect radiation. The ML structure contains a plurality of interleaving film pairs. Each film pair includes a first film and a second film. The first film and the second film have different material compositions. Each film pair has a respective thickness. For at least a subset of the plurality of the film pairs, the respective thicknesses of the film pairs change randomly along a predefined direction.