Abstract: The present disclosure provides one embodiment of a method for extreme ultraviolet lithography (EUVL) process. The method includes loading a mask to a lithography system. The mask includes defect-repaired regions and defines an integrated circuit (IC) pattern thereon. The method also includes setting an illuminator of the lithography system in an illumination mode according to the IC pattern, configuring a pupil filter in the lithography system according to the illumination mode and performing a lithography exposure process to a target with the mask and the pupil filter by the lithography system in the illumination mode.

Abstract: A method of reducing resist outgassing for EUV lithography is disclosed. The method includes forming a material layer over a substrate wherein a top surface of the material layer contains a certain concentration of a quencher or a base. The method further includes forming a resist layer over the top surface of the material layer and exposing the resist layer to a EUV radiation for patterning. The quencher or the base underneath the resist layer acts to suppress resist outgassing during the EUV exposure. The material layer itself may serve as a hard mask layer or an anti-reflection layer for the patterning process, in addition to being the carrier of the quencher or the base. The method can be used in other types of lithography, such as e-beam lithography, for reducing resist outgassing.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first layer is deposited over a substrate. A plurality of mandrels is formed over the first layer. Guiding-spacers are formed along sidewalls of the mandrels. Then the mandrels are removed. A neutral layer (NL) and a block copolymer (BCP) layer are deposited over the first layer and the guiding-spacers. A anneal is applied to the BCP layer to form a first polymer nanostructure between the guiding-spacers and being surrounded by a second polymer nanostructure. The first polymer nanostructures locate at a same distance from the first layer. Polymer nano-blocks are formed by selectively etching the second polymer nanostructure and the NL. By using the polymer nano-blocks and the guiding spacer as etch masks, the first layer is etched to form openings. The substrate is etched through the openings to form substrate trench and substrate fin.

Abstract: Provided is a method of forming a pattern for an integrated circuit. The method includes forming a first layer over a substrate, wherein the first layer's etch rate is sensitive to a radiation, such as an extreme ultraviolet (EUV) radiation or an electron beam (e-beam). The method further includes forming a resist layer over the first layer and exposing the resist layer to the radiation for patterning. During the exposure, various portions of the first layer change their etch rate in response to an energy dose of the radiation received therein. The method further includes developing the resist layer, etching the first layer, and etching the substrate to form a pattern. The radiation-sensitivity of the first layer serves to reduce critical dimension variance of the pattern.

Abstract: A reflective mask includes a substrate; a reflective multilayer formed on the substrate; an absorber layer formed on the reflective multilayer, wherein the absorber layer is patterned to have openings according to an integrated circuit layout; and a protection layer formed over the reflective multilayer within the openings.

Abstract: A Cu-containing material is provided as an absorber layer of an EUV mask. With the absorber layer of the Cu-containing material, the same lithography performance of a conventional absorber in 70 nm thickness of TaBN can be achieved by only a 30-nm thickness of the absorber layer according to the various embodiments of the present disclosure. Furthermore, the out-off-band (OOB) flare of the radiation light in 193-257 nm can be reduced so as to achieve the better lithography performance.

Abstract: An extreme ultraviolet lithography (EUVL) process is disclosed. The process comprises receiving a mask. The mask includes a low thermal expansion material (LTEM) substrate, a reflective multilayer (ML) over one surface of the LTEM substrate, a first region having a phase-shifting layer over the reflective ML, and a second region having no phase-shifting layer over the reflective ML. The EUVL process also comprises exposing the mask by a nearly on-axis illumination with partial coherence less than 0.3 to produce diffracted light and non-diffracted light, removing at least a portion of the non-diffracted light, and collecting and directing the diffracted light and the not removed non-diffracted light by a projection optics box (POB) to expose a target.

Abstract: A method of reducing resist outgassing for EUV lithography is disclosed. The method includes forming a material layer over a substrate wherein a top surface of the material layer contains a certain concentration of a quencher or a base. The method further includes forming a resist layer over the top surface of the material layer and exposing the resist layer to a EUV radiation for patterning. The quencher or the base underneath the resist layer acts to suppress resist outgassing during the EUV exposure. The material layer itself may serve as a hard mask layer or an anti-reflection layer for the patterning process, in addition to being the carrier of the quencher or the base. The method can be used in other types of lithography, such as e-beam lithography, for reducing resist outgassing.

Abstract: An extreme ultraviolet lithography (EUVL) process is performed on a target, such as a semiconductor wafer, having a photosensitive layer. The method includes providing a one-dimensional patterned mask along a first direction. The patterned mask includes a substrate including a first region and a second region, a multilayer mirror above the first and second regions, an absorption layer above the multilayer mirror in the second region, and a defect in the first region. The method further includes exposing the patterned mask by an illuminator and setting the patterned mask and the target in relative motion along the first direction while exposing the patterned mask. As a result, an accumulated exposure dose received by the target is an optimized exposure dose.

Abstract: Embodiments of EUV photomasks and methods for forming a EUV photomask are provided. The method comprises providing a substrate, a reflective layer, a capping layer, a hard mask layer, and forming an opening therein. An absorber layer is then filled in the opening and over the top surface of the hard mask layer. A removing process is provided to form an absorber with a top surface lower than a top surface of the capping layer.

Abstract: An out-of-band (OoB) suppression layer is applied on a reflective multiplayer (ML) coating, so as to avoid the OoB reflection and to enhance the optical contrast at 13.5 nm. A material having a low reflectivity at wavelength of 193-257 nm, for example, silicon carbide (SiC), is used as the OoB suppression layer. A method of fabricating an EUV mask having the OoB suppression layer and a method of inspecting an EUV mask having the OoB suppression are also provided.

Abstract: The present disclosure provides a method that includes forming a first resist layer on a substrate; forming a second resist layer over the first resist layer; and performing an electron-beam (e-beam) lithography exposure process to the first resist layer and the second resist layer, thereby forming a first latent feature in the first resist layer and a second latent feature in the second resist layer.

Abstract: An extreme ultraviolet lithography (EUVL) system for patterning a semiconductor wafer includes an extreme ultraviolet (EUV) mask. The EUV mask includes first and second states, and further includes a polygon region and an open-spacing region. The polygon region includes a plurality of main polygons separated by a plurality of first fields. The open-spacing region is located outside the polygon region, and includes a plurality of sub-resolution polygon and second fields, and does not include any main polygons. The system also includes a nearly on-axis illumination (ONI) to expose the EUV mask and optics to direct diffracted lights reflected from the EUV mask towards the semiconductor wafer.

Abstract: The present disclosure provides an embodiment of a reflective mask that includes a substrate; a reflective multilayer formed on the substrate; a capping layer formed on the reflective multilayer and having a hardness greater than about 8; and an absorber layer formed on the capping layer and patterned according to an integrated circuit layout.

Abstract: The present disclosure provides one embodiment of an extreme ultraviolet (EUV) mask. The EUV mask includes a first state and a second state different from each other; a first main polygon and a second main polygon adjacent to the first main polygon; a plurality of sub-resolution assist polygons; and a field. Each of the first and second main polygons, the sub-resolution assist polygons, and the field has an associated state. The state assigned to the first main polygon is different from the state assigned to the second main polygon. The plurality of assist polygons are assigned a same state, which is different from a state assigned to the field.

Abstract: A low EUV reflectivity mask includes a low thermal expansion material (LTEM) layer, a low EUV reflectivity (LEUVR) multilayer over the LTEM layer in a first region, a high EUV reflectivity (HEUVR) multilayer over the LTEM layer in a second region and a patterned absorption layer over the LEUVR multilayer and the HEUVR multilayer.

Abstract: A system of an extreme ultraviolet lithography (EUVL) is disclosed. The system includes a mask having reflective phase-shift-grating-blocks (PhSGBs). The system also includes an illumination to expose the mask to produce a resultant reflected light from the mask. The resultant reflected light contains mainly diffracted lights. The system also has projection optics to collect and direct resultant reflected light to expose a target.

Abstract: An extreme ultraviolet lithography (EUVL) process is performed on a target, such as a semiconductor wafer, having a photosensitive layer. The method includes providing a one-dimensional patterned mask along a first direction. The patterned mask includes a substrate including a first region and a second region, a multilayer mirror above the first and second regions, an absorption layer above the multilayer mirror in the second region, and a defect in the first region. The method further includes exposing the patterned mask by an illuminator and setting the patterned mask and the target in relative motion along the first direction while exposing the patterned mask. As a result, an accumulated exposure dose received by the target is an optimized exposure dose.

Abstract: The present disclosure provides a method for extreme ultraviolet lithography (EUVL) process. The method includes loading a binary phase mask (BPM) to a lithography system, wherein the BPM includes two phase states and defines an integrated circuit (IC) pattern thereon; setting an illuminator of the lithography system in an illumination mode according to the IC pattern; configuring a pupil filter in the lithography system according to the illumination mode; and performing a lithography exposure process to a target with the BPM and the pupil filter by the lithography system in the illumination mode.

Abstract: A system of an extreme ultraviolet lithography (EUVL) is disclosed. The system includes a mask having first and second reflective regions. The system also includes an illumination to expose the mask to produce a resultant reflected light form the mask. The resultant reflected light is constructed by a first reflected light reflected from the first reflective region and a second reflected light reflected from the second reflective region. The resultant reflected light contains mainly diffracted light. The system also a projection optics box (POB) to collect and direct resultant reflected light to expose a target.