Abstract: An electrostatic discharge (ESD) blocking circuit including an internal circuit, a first Schottky diode, and an ESD releasing element is provided. The first Schottky diode is coupled between a specific node and the internal circuit. The ESD releasing element is coupled between the specific node and the first power terminal. In response to an ESD event occurring at the specific node, the ESD releasing element is turned on to release the ESD current from the specific node to the first power terminal.

Abstract: A control circuit applied in a specific element and including a first transistor and an electrostatic discharge (ESD) protection circuit is provided. The specific element has a III-V semiconductor material and includes a control electrode, a first electrode and a second electrode. The first transistor is coupled between the first electrode and the second electrode and has the III-V semiconductor material. The ESD protection circuit is coupled to the control electrode, the first transistor and the second electrode. In response to an ESD event, the ESD protection circuit provides a discharge path to release the ESD current from the control electrode to the second electrode.

Abstract: An electrostatic discharge (ESD) blocking circuit including an internal circuit, a first Schottky diode, and an ESD releasing element is provided. The first Schottky diode is coupled between a specific node and the internal circuit. The ESD releasing element is coupled between the specific node and the first power terminal. In response to an ESD event occurring at the specific node, the ESD releasing element is turned on to release the ESD current from the specific node to the first power terminal.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate disposed on the semiconductor substrate. The semiconductor device structure also includes a source doped region and a drain doped region on two opposite sides of the gate. The semiconductor device structure further includes a source protective circuit and a drain protective circuit. From a side perspective view, a first drain conductive element of the source protective circuit partially overlaps a first source conductive element of the drain protective circuit.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first well region that has first conductive type therein. The semiconductor device structure also includes a first doped region embedded in the first well region, and having a second conductive type that is different from the first conductive type. The semiconductor device structure further includes a second well region that has the second conductive type. In addition, the semiconductor device structure includes a first metal electrode disposed on the first doped region of the semiconductor substrate and a second metal electrode disposed on the second well region of the semiconductor substrate.

Abstract: A method for forming a semiconductor device includes forming a first guard ring around at least one transistor over a substrate. The method further includes forming a second guard ring around the first guard ring, wherein the second guard ring directly contacts the first guard ring. The method further includes forming an isolation structure between the first guard ring and the second guard ring. The method further includes forming a first doped region adjacent to the first guard ring, the first doped region having a first dopant type. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having a second dopant type.

Abstract: A method for forming an integrated circuit includes forming a first guard ring around at least one transistor over a substrate. The method further includes forming a second guard ring around the first guard ring. The method further includes forming a first doped region adjacent to the first guard ring, the first doped region having a first dopant type. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having a second dopant type.

Abstract: A semiconductor device includes a SOI substrate, first and second active elements, and an interconnect structure. The SOI substrate includes a semiconductor layer which includes first and second semiconductor blocks separated from each other by an isolation structure. The first and second active elements are disposed on the first and second semiconductor blocks respectively. A source/drain region of the first active element is electrically connected to a gate structure of the second active element through a first path provided by the interconnect structure. The second semiconductor block is electrically connected to the second semiconductor block through a second path provided by the interconnect structure. The second path includes a contact that is in contact with the upper surface of the second semiconductor block.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a metal layer, a gate, a drain, a source and a first doping region. The substrate has a first doping type. The metal layer is adjacent to the surface of the substrate. The gate is formed on the substrate. The drain is formed in the substrate and located at one side of the gate. The drain is adjacent to the metal layer. The source is formed in the substrate and located at another side of the gate. The first doping region is formed in the substrate and surrounds the metal layer and the drain. The first doping region has a second doping type. The second doping type is different from the first doping type.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a metal layer, a gate, a drain, a source and a first doping region. The substrate has a first doping type. The metal layer is adjacent to the surface of the substrate. The gate is formed on the substrate. The drain is formed in the substrate and located at one side of the gate. The drain is adjacent to the metal layer. The source is formed in the substrate and located at another side of the gate. The first doping region is formed in the substrate and surrounds the metal layer and the drain. The first doping region has a second doping type. The second doping type is different from the first doping type.

Abstract: A method for forming an integrated circuit includes forming a first guard ring around at least one transistor over a substrate. The method further includes forming a second guard ring around the first guard ring. The method further includes forming a first doped region adjacent to the first guard ring, the first doped region having a first dopant type. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having a second dopant type.

Abstract: An integrated circuit includes at least one transistor over a substrate, and a first guard ring disposed around the at least one transistor. The integrated circuit further includes a second guard ring disposed around the first guard ring. The integrated circuit further includes a first doped region disposed adjacent to the first guard ring, the first doped region having a first dopant type. The integrated circuit further includes a second doped region disposed adjacent to the second guard ring, the second doped region having a second dopant type.

Abstract: An integrated circuit includes at least one transistor over a substrate, and a first guard ring disposed around the at least one transistor. The integrated circuit further includes a second guard ring disposed around the first guard ring. The integrated circuit further includes a first doped region disposed adjacent to the first guard ring, the first doped region having a first dopant type. The integrated circuit further includes a second doped region disposed adjacent to the second guard ring, the second doped region having a second dopant type.

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

Abstract: Protecting non-planar output transistors from electrostatic discharge (ESD) events includes providing a non-planar semiconductor structure, the structure including a semiconductor substrate with a well of n-type or p-type. The provided non-planar structure further includes raised semiconductor structure(s) coupled to the substrate, non-planar transistor(s) of a type opposite the well, each transistor being situated on one of the raised structure(s), the non-planar transistor(s) each including a source, a drain and a gate, the non-planar structure further including parasitic bipolar junction transistor(s) (BJT(s)) on the raised structure(s), each BJT including a collector and an emitter situated on the raised structure and a base being the well, and a well contact for the base of the BJT.

Abstract: A silicon controlled rectifier includes: a substrate; a N well and a P well positioned on a side of the substrate and contact with each other; a first N region and a first P region positioned on an upper surface of the N well and contact with each other; a second N region and a second P region positioned on an upper surface of the P well and contact with each other; a first oxide isolation region isolating the first P region and the second N region; a second oxide isolation region isolating the second N region and the second P region; an anode terminal coupled with the first N region and the first P region; and a cathode terminal coupled with the second N region and the second P region. The first P region has a doping concentration less than 80% of that of the second P region.

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

Abstract: An integrated circuit includes at least one transistor over a substrate, and a first guard ring disposed around the at least one transistor. The integrated circuit further includes a second guard ring disposed around the first guard ring. The integrated circuit further includes a first doped region disposed adjacent to the first guard ring, the first doped region having a first dopant type. The integrated circuit further includes a second doped region disposed adjacent to the second guard ring, the second doped region having a second dopant type.

Abstract: A method for forming an integrated circuit. The method includes forming a first guard ring around at least one transistor over a substrate, the first guard ring having a first type dopant. The method further includes forming a second guard ring around the first guard ring, the second guard ring having a second type dopant. The method includes forming a first doped region adjacent to the first guard ring, the first doped region having the second type dopant. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having the first type dopant, wherein the first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).