Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

Abstract: Embodiments of the invention relate to an electrostatic discharge (ESD) device and method for forming an ESD device. An embodiment is an ESD protection device comprising a p well disposed in a substrate, an n well disposed in the substrate, a high voltage n well (HVNW) disposed between the p well and the n well in the substrate, a source n+ region disposed in the p well, and a plurality of drain n+ regions disposed in the n well.

Abstract: Embodiments of the invention relate to an electrostatic discharge (ESD) device and method for forming an ESD device. An embodiment is an ESD protection device comprising a p well disposed in a substrate, an n well disposed in the substrate, a high voltage n well (HVNW) disposed between the p well and the n well in the substrate, a source n+ region disposed in the p well, and a plurality of drain n+ regions disposed in the n well.

Abstract: An ultra-high voltage device has a high voltage path established from a high voltage N-well through a first metal layer to a second metal layer, and a contact plug electrically connected between the high voltage N-well and the first metal layer. The contact plug has a distributed structure on a horizontal layout to improve the uniformity of the ultra-high voltage device such that the current in the high voltage path will be more uniform distributed so as to avoid the localized heat concentration caused by non-uniform current distribution that would damage the ultra-high voltage device. Multiple fuse apparatus are preferably connected to the first metal layer individually. Each the fuse apparatus includes a poly fuse to be burnt down when an over-load current flows therethrough.

Abstract: An integrated circuit includes at least one transistor over a substrate. A first guard ring is disposed around the at least one transistor. The first guard ring has a first type dopant. A second guard ring is disposed around the first guard ring. The second guard ring has a second type dopant. A first doped region is disposed adjacent to the first guard ring. The first doped region has the second type dopant. A second doped region is disposed adjacent to the second guard ring. The second doped region has the first type dopant. The first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).

Abstract: An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.

Abstract: A semiconductor device is provided. In an embodiment, the semiconductor device includes an inverter. The inverter is coupled to an NMOS device. The NMOS device may be protection device which protects the inverter from charging effects and/or plasma induced damage. The NMOS device may be coupled to a power source (e.g., Vss). The NMOS device may be further coupled to a capacitor. The charge of the capacitor may discharge a current through the NMOS device to the power source.

Abstract: The present invention discloses a power transistor device and a low dropout regulator (LDO) with electrostatic discharge protection. The power transistor device includes: a P-type metal oxide semiconductor (PMOS) field effect transistor (FET), having a source and a drain electrically connected to a voltage input terminal and a voltage output terminal respectively; and an electrostatic discharge protection device, electrically connected to the voltage input terminal and the voltage output terminal, for providing an electrostatic discharge path to protect the PMOSFET.

Abstract: An ultra-high voltage device has a high voltage path established from a high voltage N-well through a first metal layer to a second metal layer, and a contact plug electrically connected between the high voltage N-well and the first metal layer. The contact plug has a distributed structure on a horizontal layout to improve the uniformity of the ultra-high voltage device such that the current in the high voltage path will be more uniform distributed so as to avoid the localized heat concentration caused by non-uniform current distribution that would damage the ultra-high voltage device. Multiple fuse apparatus are preferably connected to the first metal layer individually. Each the fuse apparatus includes a poly fuse to be burnt down when an over-load current flows therethrough.

Abstract: An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.

Abstract: Electrostatic discharge (ESD) protection in high voltage semiconductor devices is disclosed that provides enhanced current isolation between transistor drains or sources by creating an isolation island surrounding the drains or sources. This isolation island can be a higher-doped region within which the drain/source lies. The junction between the higher doping of this island region and the surrounding substrates operates to limit the amount of current that passes through the drain/source. Additionally, oxide features may be used to create an island surrounding the drain/source contact. Again, this isolating effect makes the amount of current passing through the device more uniform, which protects the device from damage due to an ESD event.

Abstract: An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.

Abstract: The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Bss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.

Abstract: An integrated circuit includes at least one transistor over a substrate. A first guard ring is disposed around the at least one transistor. The first guard ring has a first type dopant. A second guard ring is disposed around the first guard ring. The second guard ring has a second type dopant. A first doped region is disposed adjacent to the first guard ring. The first doped region has the second type dopant. A second doped region is disposed adjacent to the second guard ring. The second doped region has the first type dopant. The first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).

Abstract: The present invention relates to an electrostatic discharge (ESD) protection scheme and particularly to a string contact structure for an improved ESD performance. In an embodiment, the invention provides a method for forming an ESD protection circuit for protecting an internal circuit from damage due to an ESD voltage appearing on a pad coupled to a clamp device including a first terminal and a second terminal. The method includes forming a string contact along the first terminal and the second terminal of the clamp device. The method further includes forming one or more conductive layers on the string contact to couple the first terminal and the second terminal of the clamp device to the pad and a ground pad.

Abstract: A semiconductor device is provided. In an embodiment, the semiconductor device includes an inverter. The inverter is coupled to an NMOS device. The NMOS device may be protection device which protects the inverter from charging effects and/or plasma induced damage. The NMOS device may be coupled to a power source (e.g., Vss). The NMOS device may be further coupled to a capacitor. The charge of the capacitor may discharge a current through the NMOS device to the power source.

Abstract: A semiconductor device includes a gate electrode over a semiconductor substrate, wherein the gate electrode has a gate width direction; a source/drain region in the semiconductor substrate and adjacent the gate electrode, wherein the source/drain region has a first width in a direction parallel to the gate width direction; and a bulk pick-up region in the semiconductor substrate and abutting the source/drain region. The bulk pick-up region and the source/drain region have opposite conductivity types. The bulk pick-up region has a second width in the width direction, and wherein the second width is substantially less than the first width.

Abstract: Embodiments of the invention relate to an electrostatic discharge (ESD) device and method for forming an ESD device. An embodiment is an ESD protection device comprising a p well disposed in a substrate, an n well disposed in the substrate, a high voltage n well (HVNW) disposed between the p well and the n well in the substrate, a source n+ region disposed in the p well, and a plurality of drain n+ regions disposed in the n well.

Abstract: The present invention discloses a tie-off circuit coupled between a first potential and a gate of a MOS device whose source is connected to a second potential. The tie-off circuit includes at least one resistor and at least on diode. The resistor is coupled between the gate of the MOS device and the first potential for preventing the gate of the MOS device from floating during a normal circuit operation. The diode is coupled between the gate of the MOS device and the first potential, in parallel with the resistor, for reducing a voltage difference across a gate oxide layer of the MOS device during an electrostatic discharge (ESD) event, thereby protecting the same from ESD damage.

Abstract: An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.