Abstract: A lighting fixture configured to expand and collapse, and methods for expanding and collapsing a light fixture are disclosed. Embodiments of the lighting fixture include a lighting fixture with a movable section that collapses into at least one cavity in a base housing for storage and shipment, and extends from the cavity for operation. In the collapsed configuration the lighting fixture fits into a smaller container than when the lighting fixture is in the expanded configuration. In some embodiments a locking member locks the movable section into its extended position and can be retracted by a user by manually disengaging the locking member. Accessories and extenders that can be attached to the lighting fixture can be stored in the one or more cavities into which the movable section is stowed in the collapsed configuration.

Abstract: Disclosed are various embodiments to enhance the security of a circuit design after a global routing of the circuit design and an assignment of wire layers for the circuit design. A tree can be extracted from the circuit design. The tree can include multiple gates and location information for the gates. The tree can be perturbed by moving one or more locations of one or more gates.

Abstract: Disclosed are various embodiments for optimized sensor deployment and fault detection in the context of agricultural irrigation and similar applications. For instance, a computing device may execute a genetic algorithm (GA) routine to determine an optimal sensor deployment scheme such that a mean-time-to-failure (MTTF) for the system is maximized, thereby improving communication of sensor measurements. Moreover, in various embodiments, a centralized fault detection scheme may be employed and a soil moisture of a field can be determined by statistically inferring soil moistures at locations of faulty nodes using spatial and temporal correlations.

Abstract: Example embodiments include modular lighting fixtures and methods for forming the same. Some include light emitters and base members with mounting locations for the light emitters, the light emitters and base members being combinable in varying combinations with each combination producing a different lighting effect. Some embodiments include a light guide, such as a planar light guide, that receives and redirects light from the light emitters. Additional embodiments include a reflector with portions that are positioned near a mounting location where no light emitter is mounted when the reflector is mounted to a base member. Further embodiments include a reflector with portions that are positioned near the mounting locations when mounted to a base member, the portions being easily removed, such as with an unpowered hand tool, to avoid interference with a light emitting member mounted adjacent to where the removable portion would be if not removed from the reflector.

Abstract: Disclosed are various embodiments for reinforcement learning-based irrigation control to maintain or increase a crop yield or reduce water use. A computing device may be configured to determine an optimal irrigation schedule for a crop planted in a field by applying reinforcement learning (RL), where, for a given state of a total soil moisture, the computing device performs an action, the action comprising waiting or irrigating crop. An immediate reward may be assigned to a state-action pair, the state-action pair comprising the given state of the total soil moisture and the action performed. The computing device may instruct an irrigation system to apply irrigation to at least one crop in accordance with the optimal irrigation schedule determined, where the optimal irrigation schedule includes an amount of water to be applied at a predetermined time.

Abstract: Example embodiments include modular lighting fixtures and methods for forming the same. Some include light emitters and base members with mounting locations for the light emitters, the light emitters and base members being combinable in varying combinations with each combination producing a different lighting effect. Some embodiments include a light guide, such as a planar light guide, that receives and redirects light from the light emitters. Additional embodiments include a reflector with portions that are positioned near a mounting location where no light emitter is mounted when the reflector is mounted to a base member. Further embodiments include a reflector with portions that are positioned near the mounting locations when mounted to a base member, the portions being easily removed, such as with an unpowered hand tool, to avoid interference with a light emitting member mounted adjacent to where the removable portion would be if not removed from the reflector.

Abstract: An illustrative light fixture provides an emitter housing and a driver housing in a single fixture with an airflow channel defined between the emitter and driver housings. The airflow channel minimizes thermal conduction between the emitter and driver housings, and maximizes thermal convective cooling for at least one of the emitter housing and driver housing. The emitter housing includes vertical fins extending into the airflow chamber. The left and right sides of the emitter and driver housings define top and bottom edges that are respectively coplanar with the top and bottom edges of the vertical fins.

Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.