Abstract: A semiconductor structure manufacturing method includes: a substrate is provided, and a trench structure is formed in the substrate; a first dielectric layer is formed in the trench structure, and a top surface of the first dielectric layer is lower than a top surface of the trench structure; and a protective layer is formed in the trench structure, and the protective layers at least covers a surface of the first dielectric layer and part of a side wall of the trench structure.

Abstract: Aspects of the subject technology relate to systems, methods, and computer-readable media for detecting and marking events that occur during a fracturing operation. Data related to performance of a fracturing operation in a wellbore during performance of a stage of the fracturing operation can be accessed. An event detection algorithm for detecting a specific event during the fracturing operation can be accessed. The event detection algorithm can be applied to the data to determine whether the specific event actually occurs during at least a portion of the stage of the fracturing operation. As follows, an indication of the specific event occurring during the stage of the fracturing operation can generated if it is determined that the specific event actually occurred during the at least a portion of the stage of the fracturing operation.

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes: forming an active region on a substrate; forming at least one trench in the active region, the trench at least dividing the active region into a source region on one side of the trench and a drain region on the other side of the trench; and forming an elevated source region and an elevated drain region on the source region and the drain region respectively.

Abstract: A semiconductor device includes a substrate including a memory region and a peripheral region located at an outer side of the memory region; a memory structure located above the memory region and including a memory array and signal lines, the memory array at least including memory cells spaced apart from each other along a first direction, and the signal lines being electrically connected with the memory cells, the first direction is perpendicular to the top surface of the substrate; a peripheral structure located above the peripheral region and including peripheral stacked layers, peripheral circuits located above the peripheral stacked layer, and peripheral leads located above the peripheral circuits, one end of each peripheral lead being electrically connected with at least one of peripheral circuits, and the other end being electrically connected with at least one of signal lines.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes: a substrate is provided, the substrate being provided with a first device area and a second device area with different doping types; a gate oxide layer which covers the first device area and the second device area is formed; a gate conductive layer which covers the gate oxide layer is formed; a first gate structure is formed on the first device area, the first gate structure including the gate conductive layer and the gate oxide layer; a second gate structure is formed on the second device area, the second gate structure including the gate conductive layer and the gate oxide layer. In the first device area and the second device area, the gate conductive layer always covers the gate oxide layer.

Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes the following operations. A substrate is provided, includes a core region and a peripheral region. A preset barrier layer is formed on the substrate, and covers the core region and the peripheral region. At least a part of the preset barrier layer corresponding to the peripheral region is removed to expose a part of the substrate, and to take a reserved part of the preset barrier layer as a first barrier layer. A dielectric layer and a first conductive layer are successively formed on the first barrier layer and the substrate. A part of the dielectric layer and the first conductive layer on the first barrier layer are removed, to reserve a part of the dielectric layer and the first conductive layer on the first barrier layer closer to the peripheral region.

Abstract: A method for manufacturing a buried gate and a method for manufacturing a semiconductor device are disclosed. The method for manufacturing the buried gate includes that: a trench is provided on an active region of a substrate; a gate structure is filled in a bottom of the trench, and a trench sidewall above the gate structure is exposed; an epitaxial layer is grown on the exposed trench sidewall with an epitaxial growth process, in which the epitaxial layer does not close the trench; and an isolation layer is filled in the trench.

Abstract: The present application relates to a semiconductor device and a manufacturing method thereof. The method includes: obtaining a substrate, a first device region, a second device region and a high-k gate dielectric layer film being formed on the substrate; forming, on the substrate, a barrier layer structure covering the high-k gate dielectric layer film at the second device region; forming a covering layer film including a first metal element on the substrate; and diffusing the first metal element in the covering layer film towards the high-k gate dielectric layer film at the first device region using an annealing process, the barrier layer structure preventing the first metal element from being diffused towards the high-k gate dielectric layer film at the second device region; wherein the first device region and the second device region have opposite conduction types.

Abstract: Systems, apparatuses and methods may provide for technology that collects, by a BIOS (basic input output system), memory information from a first host path to a coherent device memory on a memory expander, wherein the memory expander includes a plurality of host paths, transfers the memory information from the BIOS to an OS (operating system) via one or more OS interface tables, and initializes, by the OS, the memory expander based on the memory information, wherein the memory information includes memory capabilities and configuration settings associated with the memory expander.

Abstract: A trajectory planning method, a computer-readable storage medium, and a robot are provided. The method includes: constructing a phase variable of a trajectory planning of a robot, where the phase variable is a function of two position components of a torso of the robot on a horizontal plane; and performing, using the phase variable replacing a time variable, the trajectory planning on a swinging leg of the robot in each preset coordinate axis direction. In this manner, the robot can no longer continue to follow the established trajectory after being disturbed by the environment, but make state adjustments according to the disturbance received to offset the impact of the disturbance, thereby maintaining walking stability and avoiding the problem of early or late landing of the swinging leg.

Abstract: A method for navigating in a simulated environment is disclosed herein. A navigation device determines a search space associated with a plurality of viewpoints other than the current viewpoint in a three-dimensional (3D) space for a current viewpoint. The search space comprises a set of 3D coordinates for each of the plurality of viewpoints. The navigation device determines a field of view at the current viewpoint, which is an area associated with a viewing angle and a visible distance. The navigation device determines a target viewpoint in the search space of the current viewpoint based on the field of view at the current viewpoint. The target viewpoint is outside the area of the field of view at the current viewpoint. The navigation device causes display of a guidance user interface (UI) comprising an indicator corresponding to the target viewpoint in the field of view at the current viewpoint.

Abstract: An apparatus for measuring mechanical properties of a rock formation. The apparatus includes force application fixtures configured to apply opposing compressive forces to a disc-shaped sample of a core plug specimen from the rock formation. Each of the force application fixtures include an applicant portion having an end cap. The end cap has a shaped surface that is configured to conform with a portion of a non-planar side of the disc-shaped sample such that substantially an entire volume of the disc-shaped sample experiences a compressive stress when the opposing compressive forces are applied to the portions of the non-planar side. A system and method for measuring mechanical properties of a rock formation are also disclosed.

Abstract: A preparation method of a semiconductor structure includes: a substrate including a groove structure is provided; a first isolation layer, a second isolation layer and a third isolation layer are sequentially formed on a bottom and sidewalls of the groove structure, where an upper surface of the first isolation layer is lower than an upper surface of the second isolation layer and an upper surface of the substrate to form a side trench; the third isolation layer is etched to enable an upper surface of the third isolation layer to be lower than the upper surface of the second isolation layer so that a top of the second isolation layer protrudes with respect to the first isolation layer and the third isolation layer to form a convex structure; and the second isolation layer is etched to remove the convex structure.

Abstract: The present disclosure relates to a patterning method and a method of manufacturing a semiconductor structure. The patterning method includes: providing a base; forming a first patterned mask layer on a surface of the base, where the first patterned mask layer includes a plurality of first mask structures extending along a first direction, and the first mask structures are arranged at intervals; forming a first dielectric layer on the first patterned mask layer, where the first dielectric layer fills up a spacing region between the first mask structures and covers an upper surface of the first patterned mask layer; and etching the first dielectric layer to form a plurality of second mask structures extending along a second direction, where the second mask structures are arranged at intervals, and the second direction intersects with the first direction; and selectively etching the first mask structure and the second mask structure.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method includes: providing a base; forming a plurality of support layers on the base, where the support layers are configured to support a plate capacitor structure, extend along a first direction, and are arranged at intervals along a second direction, and the first direction intersects the second direction; forming a bottom electrode layer, where the bottom electrode layer at least covers sidewalls of the support layers; and forming a dielectric layer, the dielectric layer covering the bottom electrode layer.

Abstract: A computer-implemented gait planning method includes: determining a pitch angle between a foot of the robot and a support surface where the robot stands; determining a support point on a sole of the foot according to the pitch angle; calculating an ankle-foot position vector according to the support point, wherein the ankle-foot position vector is a position vector from an ankle of the robot to a support point on a sole of the foot; calculating a magnitude of change of an ankle position according to the pitch angle and the ankle-foot position vector; and obtaining a compensated ankle position by compensating the ankle position according to the magnitude of change of the ankle position.

Abstract: A walking control method for a biped robot includes: detecting whether the biped robot is in an unbalanced state; in response to detection that the biped robot is in the unbalanced state, obtaining a predicted balance step length corresponding to the biped robot in the unbalanced state; performing a smooth transition processing on the predicted balance step length according to a current movement step length of the biped robot to obtain a desired balance step length corresponding to the predicted balance step length; determining a planned leg trajectory of the biped robot according to the desired balance step length; and controlling a current swing leg of the biped robot to move according to the planned leg trajectory.

Abstract: The invention relates to the field of medical biotechnology. Specifically, the present invention relates to a fusion protein containing an anti-interleukin-17 antibody and a tumor necrosis factor receptor extracellular region, a polynucleotide encoding the fusion protein, a vector comprising the polynucleotide, a host cell comprising the polynucleotide or the vector, and the use of the fusion protein for the treatment, prevention, and/or diagnosis of a related disease in an individual.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: forming a capacitor on a substrate, where a first support layer is provided between parts of the first electrodes in the capacitor away from the substrate; removing part of a second electrode and part of a first dielectric layer to expose a surface of the first support layer away from the substrate; forming, on the surface of the first support layer away from the substrate, a second support layer having a first hole structure; forming, on a side surface of the first hole structure, a third electrode in contact with the first electrode; forming a second dielectric layer covering the third electrode and being in contact with the first dielectric layer; and forming, on a side surface of the second dielectric layer, a fourth electrode in contact with the second electrode.

Abstract: A method for controlling a legged robot includes: in response to detection of a collision event associated with a foot of a swing leg of the biped robot, terminating a trajectory component planning of the swing leg in a collision direction; calculating a position offset in the collision direction according to an external force that is received by the foot of the swing leg in the collision direction and obtained in real time, based on a foot dragging control mode, and determining a replanned trajectory component in the collision direction based on the position offset; and controlling the swing leg to move based on the replanned trajectory component in the collision direction and a desired trajectory component of the swing leg in a non-collision direction.