Patents by Inventor Jie Bai

Jie Bai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220355479
    Abstract: A gait planning method and a robot using the same as well as a computer readable storage medium are provided. The method includes: determining a reference leg length l0 and a leg length variation range A of a robot; performing a trajectory planning on a length of at least one of the legs of the robot using; an equation including the reference leg length, the leg length variation range, and a preset recurrent excitation function of a time variable t. In this manner, the trajectory planning for the leg length of the robot during motion is performed according to the characteristics of motion scene such as robot jumping or running so that the change of the leg length of the robot is adapted to the motion process, which greatly improves the stability of the robot in the motion scene such as jumping or running.
    Type: Application
    Filed: February 23, 2022
    Publication date: November 10, 2022
    Inventors: Jie Bai, Yizhang Liu, Ligang Ge, Chunyu Chen, Qiuyue Luo, Youjun Xiong
  • Publication number: 20220352372
    Abstract: Embodiments of the present application provide a semiconductor device and a method of manufacturing semiconductor device. The semiconductor device includes a substrate, a silicon-germanium (SiGe) epitaxial layer, a protective layer, and a positive-channel metal-oxide semiconductor (PMOS) gate; a surface of the substrate includes at least a PMOS region; the SiGe epitaxial layer is grown on the surface of the substrate and located in the PMOS region; the protective layer covers a surface of the SiGe epitaxial layer; the PMOS gate is located on a surface of the protective layer.
    Type: Application
    Filed: November 9, 2021
    Publication date: November 3, 2022
    Inventors: Jie BAI, Wenli ZHAO
  • Publication number: 20220352175
    Abstract: The present disclosure relates to the technical field of semiconductor manufacturing, and provides a method of manufacturing a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing a substrate; forming a mask layer on the substrate; removing a part of the mask layer on a non-array region; forming a first oxide layer on the non-array region; removing a part of the first oxide layer on a first transistor region, to expose a top surface of the first transistor region; forming an epitaxial layer on the exposed top surface of the first transistor region; removing a part of the first oxide layer on a second transistor region; and forming a second oxide layer on the second transistor region and the epitaxial layer.
    Type: Application
    Filed: February 18, 2022
    Publication date: November 3, 2022
    Inventors: JIE BAI, Kang You
  • Publication number: 20220349289
    Abstract: Aspects of the subject technology relate to systems and methods for improving cluster and surface efficiency in hydraulic fracturing by utilizing a stage optimization tool. Systems and methods are provided for receiving one or more perforation parameters of a wellbore, generating a perforation schema based on the one or more perforation parameters, training a stage optimization model based on the perforation schema to generate an optimized perforation schema, estimating a pressure of the wellbore based on the optimized perforation schema, and updating the optimized perforation schema until the estimated pressure is less than a predetermined pressure limit.
    Type: Application
    Filed: April 30, 2021
    Publication date: November 3, 2022
    Inventors: Ubong Akpan INYANG, Dinesh Ananda Shetty, Srividhya Sridhar, Jie Bai, William Ruhle
  • Publication number: 20220344351
    Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes the following operations. A substrate is provided, includes a core region and a peripheral region. A preset barrier layer is formed on the substrate, and covers the core region and the peripheral region. At least a part of the preset barrier layer corresponding to the peripheral region is removed to expose a part of the substrate, and to take a reserved part of the preset barrier layer as a first barrier layer. A dielectric layer and a first conductive layer are successively formed on the first barrier layer and the substrate. A part of the dielectric layer and the first conductive layer on the first barrier layer are removed, to reserve a part of the dielectric layer and the first conductive layer on the first barrier layer closer to the peripheral region.
    Type: Application
    Filed: January 20, 2022
    Publication date: October 27, 2022
    Inventors: Mengmeng YANG, Jie Bai
  • Patent number: 11461975
    Abstract: A method for navigating in a simulated environment is disclosed herein. A navigation device determines a search space associated with a plurality of viewpoints other than the current viewpoint in a three-dimensional (3D) space for a current viewpoint. The search space comprises a set of 3D coordinates for each of the plurality of viewpoints. The set of 3D coordinates indicates a position of the corresponding viewpoint in the 3D space. The navigation device determines a field of view at the current viewpoint. The field of view is associated with a viewing angle and a visible distance. The navigation device determines a target viewpoint in the search space of the current viewpoint based on the field of view at the current viewpoint. The navigation device causes display of a guidance user interface (UI) comprising an indicator corresponding to the target viewpoint in the field of view at the current viewpoint.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: October 4, 2022
    Assignee: Realsee (Beijing) Technology Co., Ltd.
    Inventors: Yiding Wang, Chengjie Li, Jie Bai, Yi Zhu
  • Publication number: 20220310458
    Abstract: The present application relates to a semiconductor device and a manufacturing method thereof. The method includes: obtaining a substrate, a first device region, a second device region and a high-k gate dielectric layer film being formed on the substrate; forming, on the substrate, a barrier layer structure covering the high-k gate dielectric layer film at the second device region; forming a covering layer film including a first metal element on the substrate; and diffusing the first metal element in the covering layer film towards the high-k gate dielectric layer film at the first device region using an annealing process, the barrier layer structure preventing the first metal element from being diffused towards the high-k gate dielectric layer film at the second device region; wherein the first device region and the second device region have opposite conduction types.
    Type: Application
    Filed: May 25, 2021
    Publication date: September 29, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Jie BAI, Kang YOU
  • Publication number: 20220310799
    Abstract: Embodiments relate to a method for fabricating a semiconductor structure, a semiconductor structure, and a peripheral circuit. The method for fabricating a semiconductor structure includes: providing a substrate; forming a gate initial structure and a residue on the substrate; and removing the residue by means of a first cleaning liquid. The first cleaning liquid is capable of inhibiting the residue from undergoing a hydrolysis reaction.
    Type: Application
    Filed: September 7, 2021
    Publication date: September 29, 2022
    Inventors: Jie BAI, Kang YOU
  • Publication number: 20220293611
    Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure can improve performance of the semiconductor structure. The method for manufacturing the semiconductor structure includes: forming bit line structures on a substrate, each of the bit line structures including a conductive layer, a transition layer and a covering layer stacked sequentially, and a width of the transition layer being smaller than a width of the conductive layer; and forming air gaps on a top surface of the conductive layer and side surfaces of the transition layer. The air gaps not only can reduce influence of the covering layer on the conductive layer to prevent the resistance of the conductive layer from increasing, but also can reduce the parasitic capacitance between the bit line structures and the surrounding structures thereof, thereby improving the performance of the semiconductor structure.
    Type: Application
    Filed: December 7, 2021
    Publication date: September 15, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: ER-XUAN PING, JIE BAI, Juanjuan HUANG
  • Publication number: 20220293610
    Abstract: Provided are a manufacturing method of a semiconductor structure, and a semiconductor structure. The manufacturing method includes: providing a substrate; forming a plurality of bit line structures distributed at intervals on the substrate, each of the bit line structures including a conductive structure, a conductive barrier block and an insulative structure which are stacked sequentially, and the width of the conductive barrier block being less than the width of the conductive structure; and forming an air gap in contact with a side wall of each of the bit line structures.
    Type: Application
    Filed: January 14, 2022
    Publication date: September 15, 2022
    Inventors: ER-XUAN PING, Jie Bai, Juanjuan Huang
  • Publication number: 20220284680
    Abstract: A method for navigating in a simulated environment is disclosed herein. A navigation device determines a search space associated with a plurality of viewpoints other than the current viewpoint in a three-dimensional (3D) space for a current viewpoint. The search space comprises a set of 3D coordinates for each of the plurality of viewpoints. The navigation device determines a field of view at the current viewpoint, which is an area associated with a viewing angle and a visible distance. The navigation device determines a target viewpoint in the search space of the current viewpoint based on the field of view at the current viewpoint. The target viewpoint is outside the area of the field of view at the current viewpoint. The navigation device causes display of a guidance user interface (UI) comprising an indicator corresponding to the target viewpoint in the field of view at the current viewpoint.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 8, 2022
    Inventors: Yiding WANG, Chengjie LI, Jie BAI, Yi ZHU
  • Publication number: 20220223412
    Abstract: A method for preparing a semiconductor structure includes: providing a substrate which includes a device region and a shallow trench isolation region surrounding the device region, in which the device region is exposed from a surface of the substrate; depositing a barrier layer on the substrate, the barrier layer at least covering the device region; forming an initial oxide which is located in the device region and in contact with the barrier layer; and removing part of the initial oxide to form a device oxide.
    Type: Application
    Filed: August 4, 2021
    Publication date: July 14, 2022
    Inventors: Mengmeng YANG, Jie BAI
  • Publication number: 20220223419
    Abstract: A method for manufacturing a semiconductor structure includes: forming a first diffusion film layer on a dielectric layer, a thickness of the first diffusion film layer being not less than a thickness of a doped layer; forming a hard mask on the first diffusion film layer; etching each film layer corresponding to a first region and a second region toward a substrate, until the first diffusion film layer corresponding to the first region is exposed; and next, removing a first metal oxide layer remaining on the dielectric layer corresponding to the second region. As a result of the presence of the doped layer, the hard mask corresponding to the second region has a relatively small thickness.
    Type: Application
    Filed: September 8, 2021
    Publication date: July 14, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: JIE BAI, Kang YOU
  • Publication number: 20220223420
    Abstract: A manufacturing method for a semiconductor structure includes: a substrate is provided, the substrate including a first region and a second region; a dielectric layer is formed on the substrate; a first diffusion film layer having a first metal oxide layer is formed on the dielectric layer; the first diffusion film layer corresponding to the second region is removed; a second diffusion film layer is formed on the dielectric layer corresponding to the second region, the second diffusion film layer including a second metal oxide layer interfacing with the dielectric layer; and an annealing treatment is performed to diffuse a first metal element in the first metal oxide layer into the dielectric layer corresponding to the first region and diffuse a second metal element in the second metal oxide layer into the dielectric layer corresponding to the second region.
    Type: Application
    Filed: October 20, 2021
    Publication date: July 14, 2022
    Inventors: Mengmeng YANG, JIE BAI
  • Publication number: 20220223421
    Abstract: A manufacturing method for a semiconductor structure of the disclosure includes: a first stack layer is formed; a sacrificial layer is provided on the first stack layer; thermal annealing treatment is performed on the first stack layer and the sacrificial layer so that the first stack layer is formed into a second stack layer; the sacrificial layer and a work function composite layer and a first conductive layer of the second stack layer are removed, and a substrate, a second interface layer and a high-k layer of the second stack layer are retained; and a gate layer is formed on the high-k layer.
    Type: Application
    Filed: September 9, 2021
    Publication date: July 14, 2022
    Inventors: Mengmeng YANG, Jie BAI
  • Publication number: 20220223603
    Abstract: A method of manufacturing a semiconductor structure and a semiconductor structure are disclosed in embodiments of the present disclosure. The method of manufacturing a semiconductor includes: providing a base; and forming an electrical contact layer, a bottom barrier layer, and a conductive layer that are sequentially stacked on the base, where a material of the conductive layer includes molybdenum.
    Type: Application
    Filed: February 7, 2022
    Publication date: July 14, 2022
    Inventors: Er-Xuan Ping, Jie Bai, Juanjuan Huang
  • Publication number: 20220216097
    Abstract: A semiconductor structure manufacturing method includes: a substrate is provided, and a trench structure is formed in the substrate; a first dielectric layer is formed in the trench structure, and a top surface of the first dielectric layer is lower than a top surface of the trench structure; and a protective layer is formed in the trench structure, and the protective layers at least covers a surface of the first dielectric layer and part of a side wall of the trench structure.
    Type: Application
    Filed: October 1, 2021
    Publication date: July 7, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Kang YOU, JIE BAI
  • Publication number: 20220203534
    Abstract: A path planning method and a biped robot using the same are provided. The method includes: generating a candidate node set for a next foot placement based on a biped robot's own parameters and joint information of a current node, adding valid candidate nodes in the candidate node set to a priority queue so as to select optimal nodes for realizing next node expansion. These optimal nodes are output to generate a foot placement sequence from an initial node to a target node, which can greatly reduce the search amount for path nodes when the robot's legs intersect and touch the ground, thereby improving the efficiency of path planning.
    Type: Application
    Filed: November 2, 2021
    Publication date: June 30, 2022
    Inventors: Xingxing Ma, Chunyn Chen, Ligang Ge, Yizhang Liu, Hongge Wang, Jie Bai, Zheng Xie, Jiangchen Zhou, Meihui Zhang, Shuo Zhang, Youjun Xiong
  • Publication number: 20220206501
    Abstract: A dynamic footprint set generation method, a biped robot using die same, and a computer readable storage medium are provided. The method includes: obtaining preset footprint calculation parameters; calculating a landing point position based on the preset footprint calculation parameters; determining a landing point range based on a landing point position, and performing a collision detection on the landing point range; recording the corresponding landing point position in a footprint set in response to the detection result representing there being no collision; obtaining a preset adjustment amplitude to update a preset displacement angle after the recording is completed; and returning to the calculating the landing point position until the footprint set is generated.
    Type: Application
    Filed: August 31, 2021
    Publication date: June 30, 2022
    Inventors: Xingxing Ma, Chunyu Chen, Yizhang Liu, Ligang Ge, Hongge Wang, Jie Bai, Jiangchen Zhou, Zheng Xie
  • Publication number: 20220208974
    Abstract: In a method for manufacturing a semiconductor structure, a substrate is provided; a stack layer is formed on the substrate, the stack layer including an interfacial layer, a high-k dielectric layer and a work function composite layer which are sequentially stacked; a transition layer is formed on the stack layer; and a metal gate layer is formed on the transition layer. The work function composite layer is prepared by a physical vapor deposition process.
    Type: Application
    Filed: August 23, 2021
    Publication date: June 30, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Mengmeng YANG, Jie BAI