Patents by Inventor Jie Lin

Jie Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230299088
    Abstract: Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate directly connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate directly connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate directly connected to the second node. A second NMOS transistor is coupled between the first node and the ground, and has a gate directly connected to the first node. Sources of the first and second NMOS transistors share an N+ doped region in the P-type well region. The first NMOS transistor is disposed between the second NMOS transistor and the first and second PMOS transistors. Source of the first PMOS transistor is directly connected to the power supply.
    Type: Application
    Filed: April 14, 2023
    Publication date: September 21, 2023
    Inventors: Chien-Yao HUANG, Wun-Jie LIN, Chia-Wei HSU, Yu-Ti SU
  • Publication number: 20230295285
    Abstract: Methods are provided for improved treatment of subjects with cancer anorexia-cachexia syndrome, comprising treatment with a combination of at least one anti-cancer agent and at least one GDF15 modulator. Methods are further provided for improved treatment of subjects with anti-cancer agents which induce cachexia, comprising further treating the subject with at least one GDF15 modulator.
    Type: Application
    Filed: September 7, 2022
    Publication date: September 21, 2023
    Inventors: Jeno Gyuris, Lorena Lerner, Jie Lin
  • Publication number: 20230291628
    Abstract: This disclosure provides a carrier signal processing method and apparatus. In the method, clipping factors are determined based on scheduling information corresponding to at least two respective carrier signals in a first time unit, the clipping factors correspond to the at least two respective carrier signals in the first time unit and are used for clipping processing a combination signal of the at least two carrier signals in the first time unit. The at least two carrier signals and the clipping factors are sent to a radio unit for processing. In this solution, clipping factors are matched in real time with scheduling information respectively corresponding to a plurality of carrier signals in the first time unit, to improve clipping performance.
    Type: Application
    Filed: May 23, 2023
    Publication date: September 14, 2023
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Zhengwei Gong, Yongchao Pan, Shiguo Guan, Jie Lin
  • Patent number: 11756953
    Abstract: A semiconductor device includes a P-doped well having a first concentration of P-type dopants in the substrate; a P-doped region having a second concentration of P-type dopants in the substrate and extending around a perimeter of the P-doped well; a shallow trench isolation structure (STI) between the P-doped well and the P-doped region; an active area on the substrate, the active area including an emitter region and a collector region; a deep trench isolation structure (DTI) extending through the active area and between the emitter region and the collector region; and an electrical connection between the emitter region and the P-doped region.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Hao Chiang, Wun-Jie Lin, Jam-Wem Lee
  • Patent number: 11749673
    Abstract: Systems and methods for protecting a device from an electrostatic discharge (ESD) event are provided. A resistor-capacitor (RC) trigger circuit and a driver circuit are provided. The RC trigger circuit is configured to provide an ESD protection signal to the driver circuit. A discharge circuit includes a first metal oxide semiconductor (MOS) transistor and a second MOS transistor connected in series between a first voltage potential and a second voltage potential. The driver circuit provides one or more signals for turning the first and second MOS transistors on and off.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shu-Yu Su, Jam-Wem Lee, Wun-Jie Lin
  • Publication number: 20230275628
    Abstract: Embodiments of this application provide antenna switching methods and apparatuses. In an implementation, a first communication device determines a first antenna identifier based on air interface transmission information, the first communication device sends the first antenna identifier to a digital switch, and the digital switch switches from a second switch state to a first switch state based on the first antenna identifier, where the first switch state indicates that a second communication device communicates with the first antenna within a first time unit, and the second switch state indicates that the second communication device communicates with a second antenna within a second time unit.
    Type: Application
    Filed: May 4, 2023
    Publication date: August 31, 2023
    Inventors: Chenhui GE, Linlin WANG, Liang LI, Haizheng TANG, Jie LIN, Jiachong ZHOU, Xiaoguang SUN, Shiguo GUAN
  • Patent number: 11740406
    Abstract: A circuit for detecting an optical data signal includes a photonics substrate and first and second photodiodes formed in the photonics substrate. The first photodiode is configured to receive, via an input port formed in the photonics substrate, a first portion of the optical data signal and convert light power of the first portion of the optical data signal to generate a first current based on the optical data signal. The second photodiode is configured to output a second current without receiving any portion of the optical data signal. The second current corresponds to a dark current induced in the second photodiode. The circuit is configured to subtract the second current from the first current to generate an output signal corresponding to a power of the optical data signal without dark current induced in the first photodiode.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: August 29, 2023
    Assignee: Marvell Asia Pte Ltd.
    Inventors: Jie Lin, Masaki Kato, Bruno Tourette, Brian Taylor
  • Publication number: 20230261003
    Abstract: An integrated circuit (IC) device includes a plurality of first doped regions of a first semiconductor type over at least one first well region of the first semiconductor type, and a second doped region of a second semiconductor type over a second well region of the second semiconductor type. The second semiconductor type is different from the first semiconductor type. The plurality of first doped regions is arranged along a first direction. Each of the plurality of first doped regions has a first length in the first direction. The second doped region extends in the first direction between at least two first doped regions among the plurality of first doped regions over a second length greater than the first length.
    Type: Application
    Filed: April 25, 2023
    Publication date: August 17, 2023
    Inventors: Chien Yao HUANG, Wun-Jie LIN, Kuo-Ji CHEN
  • Patent number: 11728330
    Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Yeh, Wun-Jie Lin, Jam-Wem Lee
  • Publication number: 20230247286
    Abstract: Embodiments of this application provide a photographing method and an electronic device, and relate to the field of electronic technologies. The photographing method and the electronic device may provide a captured image with a large aperture background blurring effect, and improve clarity of an object at a focus and a blurring effect of a background part. The method is applied to the electronic device, and the electronic device includes a first camera, a second camera, and a third camera.
    Type: Application
    Filed: March 18, 2022
    Publication date: August 3, 2023
    Inventors: Hantao Cui, Yang Yang, Shuai Feng, Jie Lin, Lingli Chang
  • Publication number: 20230237237
    Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.
    Type: Application
    Filed: March 27, 2023
    Publication date: July 27, 2023
    Inventors: Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su, Mohammed Rabiul Islam, Shu-Yi Ying, Stefan Rusu, Kuan-Te Li, David Barry Scott
  • Publication number: 20230238793
    Abstract: An electrostatic discharge (ESD) protection circuit includes a first diode, a second diode, an ESD clamp circuit and a first conductive structure on a backside of a semiconductor wafer, and being coupled to the first voltage supply. The first diode is in the semiconductor wafer, and coupled between an IO pad and a first node. The second diode is in the semiconductor wafer, coupled to the first diode and coupled between the IO pad and a second node. The ESD clamp circuit is in the semiconductor wafer, coupled between the first node and the second node, and further coupled to the first and second diode. The ESD clamp circuit includes a first signal tap region in the semiconductor wafer that is coupled to a first voltage supply. The first diode is coupled to and configured to share the first signal tap region with the ESD clamp circuit.
    Type: Application
    Filed: March 30, 2023
    Publication date: July 27, 2023
    Inventors: Yu-Hung YEH, Wun-Jie LIN, Jam-Wem LEE
  • Publication number: 20230203802
    Abstract: A column cap connector for mounting and securing a beam to a post of a building including a central web portion and upwardly extending walls disposed along longitudinal edges thereof, wherein a lower portion of the beam fits within the walls, downwardly extending legs formed from the seat and alternatively from the seat and the walls of the connector attach the connector to the post with projecting tabs attached to the seat to support the connector on the post.
    Type: Application
    Filed: March 6, 2023
    Publication date: June 29, 2023
    Inventors: Sam Thomas Hensen, Emmet J. Mielbrecht, Timothy M. Stauffer, Jin-Jie Lin
  • Publication number: 20230205337
    Abstract: The disclosure provides a border touch module, including a cover plate, a shielding layer, a first adhesive layer, a sensing electrode layer, a second adhesive layer, an opaque adhesive, and a backlight layer. The shielding layer is disposed below the cover plate. The first adhesive layer is disposed below the shielding layer. The sensing electrode layer is disposed below the first adhesive layer. The second adhesive layer is disposed below the sensing electrode layer. The opaque adhesive is disposed below the sensing electrode layer. The backlight layer is disposed below the opaque adhesive and is in the same plane as the second adhesive layer. The shielding layer has a backlight pattern, and the opaque adhesive has a light source hole. When the backlight layer is in the state of driving backlight, the light illuminates the backlight pattern of the shielding layer through the light source hole.
    Type: Application
    Filed: January 13, 2023
    Publication date: June 29, 2023
    Inventors: Ching-Kai CHO, Zhi Juan LIN, Ting-Chieh CHIEN, Wei Jie LIN, Hua Li LUO
  • Patent number: 11686991
    Abstract: A silicon optical modulator includes a silicon-on-insulator substrate and a first waveguide and a second waveguide arranged parallel to each other in the silicon-on-insulator substrate. The first waveguide includes a first PN junction. The second waveguide includes a second PN junction. At least one of the first PN junction and the second PN junction is disposed at an interface between a P type doped region and a N type doped region. The interface has an irregular shape that is not perpendicular to a plane in which the silicon-on-insulator substrate lies.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: June 27, 2023
    Assignee: MARVELL ASIA PTE LTD
    Inventors: Xiaoguang Tu, Jie Lin, Masaki Kato
  • Patent number: 11686885
    Abstract: Compound eyes of insects are great optical system for imaging and sensing by the nature creator, which is an unsurpassed challenge due to its precision and small size. Here, we use meta-lens consisting of GaN nano-antenna to open the fascinating doorway to full-color achromatic light field imaging and sensing. A 60×60 multi-channels meta-lens array is used for effectively capturing multi-dimensional optical information including image and depth. Based on this, the multi-dimensional light field imaging and sensing of a moving object is capable to be experimentally implemented. Our system presents a diffraction-limit resolution of 1.95 micrometer via observing the standard resolution test chart under white light illumination. This is the first mimic optical light field imaging and sensing system of insect compound eye, which has potential applications in micro robotic vision, non-men vehicle sensing, virtual and augmented reality, etc.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: June 27, 2023
    Assignee: ACADEMIA SINICA
    Inventors: Din-Ping Tsai, Cheng-Hung Chu, Ren-Jie Lin, Mu-Ku Chen, Pin-Chieh Wu
  • Patent number: 11675337
    Abstract: A system for acceleration adjustment of machine tool at rapid traverse includes a signal measurement module, a signal judgment module and an acceleration optimization module. The machine tool has a servo motor and a working platform. The signal measurement module measures signals while the servo motor drives the working platform from a first specific position to a second specific position, or from the second specific position back to the first specific position. The signal judgment module judges whether the actual maximum current value of the motor is equal to the manufacturer's specification according to the signals; and if negative, the acceleration optimization module calculates and optimizes an axial acceleration till an optimal value is achieved. Then, a curve smoothing time of the optimal acceleration is calculated and optimized by the acceleration optimization module. In addition, a method for acceleration adjustment of machine tool at rapid traverse is provided.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: June 13, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jheng-Jie Lin, Kuo-Hua Chou, Chien-Chih Liao, Jen-Ji Wang
  • Publication number: 20230167422
    Abstract: Provided is a parent phytase variant, which relates to the technical field of protein engineering. The variant, relative to the parent phytase thereof, has one or more amino acid substitutions at positions corresponding to positions 295, 349, and 374 of SEQ ID NO: 1. Compared to the parent phytase, the variant has increased thermal stability.
    Type: Application
    Filed: February 3, 2021
    Publication date: June 1, 2023
    Inventors: Jie Lin, Aixi Bai, Ke Huang, Yan Sun, Hong Xu
  • Publication number: 20230169782
    Abstract: A cabin monitoring and situation understanding perceiving method is proposed. A cabin interior image capturing step is performed to capture a cabin interior image. A generative adversarial network model creating step is performed to create a generative adversarial network model according to the cabin interior image. An image adjusting step is performed to adjust the cabin interior image to generate an approximate image. A cabin interior monitoring step is performed to process the approximate image to generate a facial recognizing result and a human pose estimating result. A cabin exterior image and voice capturing step is performed to capture a cabin exterior image and a voice information. A situation understanding perceiving step is performed to process at least one of the approximate image, the cabin exterior image and the voice information according to a situation understanding model to perceive a situation understanding result.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 1, 2023
    Inventor: Yi-Jie LIN
  • Publication number: 20230169747
    Abstract: A feature point integration positioning system includes a moving object, an image input source, an analyzing module and a positioning module. The image input source is disposed at the moving object to shoot an environment for obtaining a sequential image dataset. The analyzing module includes a machine vision detecting unit configured to generate a plurality of first feature points in each of the images based on each of the images, a deep learning detecting unit configured to generate a plurality of second feature points in each of the images based on each of the images, and an integrating unit configured to integrate the first feature points and the second feature points in each of the images into a plurality of integrated feature points in each of the images. The positioning module confirms a position of the moving object relative to the environment at each of the time points.
    Type: Application
    Filed: November 29, 2021
    Publication date: June 1, 2023
    Inventors: Yu-Fang WANG, Yi-Jie LIN, Cheng-Kai WANG