Abstract: A printing method and a printing system are provided. When printing a file on a client, the client is connected to a printer via a network. A print homepage is shown to the client. Then the client accesses the printer via the print homepage on the client, and sends an coded file to the printer. The printer receives the coded file from the client, and decodes the file to print. The printing system includes a client and a printer. An coded file is stored in the client. The client includes an internet browser. The printer includes a file receiving module to receive the file from the client and a print controlling module capable of controlling the printer to decode and print the coded file. A print homepage is shown on the internet browser. The client accesses the printer and sends the coded file to the printer via the print homepage.

Abstract: A solid solution-comprising ceramic article useful in semiconductor processing, which is resistant to erosion by halogen-containing plasmas. The solid solution-comprising ceramic article is formed from a combination of yttrium oxide and zirconium oxide. In a first embodiment, the ceramic article includes ceramic which is formed from yttrium oxide at a molar concentration ranging from about 90 mole % to about 70 mole %, and zirconium oxide at a molar concentration ranging from about 10 mole % to about 30 mole %. In a second embodiment, the ceramic article includes ceramic which is formed from zirconium oxide at a molar concentration ranging from about 96 mole % to about 94 mole %, and yttrium oxide at a molar concentration ranging from about 4 mole % to about 6 mole %.

Abstract: A method of controlling fault currents within a utility power grid is provided. The method may include coupling a superconducting electrical path between a first and a second node within the utility power grid and coupling a non-superconducting electrical path between the first and second nodes within the utility power grid. The superconducting electrical path and the non-superconducting electrical path may be electrically connected in parallel. The superconducting electrical path may have a lower series impedance, when operated below a critical current level, than the non-superconducting electrical path. The superconducting electrical path may have a higher series impedance, when operated at or above the critical current level, than the non-superconductor electrical path.

Abstract: A superconducting transformer system is configured to be included within a utility power grid having a known fault current level. The superconducting transformer system includes a non-superconducting transformer interconnected between a first node and a second node of the utility power grid. A superconducting transformer is interconnected between the first node and the second node of the utility power grid. The superconducting transformer and the non-superconducting transformer are electrically connected in parallel. The superconducting transformer has a lower series impedance than the non-superconducting transformer when the superconducting transformer is operated below a critical current level and a critical temperature. The superconducting transformer is configured to have a series impedance that is at least N times the series impedance of the non-superconducting transformer when the superconducting transformer is operated at or above one or more of the critical current level and the critical temperature.

Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

Abstract: A method of fabricating doped quartz component is provided herein. In one embodiment, the doped quartz component is a yttrium doped quartz ring configured to support a substrate. In another embodiment, the doped quartz component is a yttrium and aluminum doped cover ring. In yet another embodiment, the doped quartz component is a yttrium, aluminum and nitrogen containing cover ring.

Abstract: A ceramic article which is resistant to erosion by halogen-containing plasmas used in semiconductor processing. The ceramic article includes ceramic which is multi-phased, typically including two phase to three phases. The ceramic is formed from yttrium oxide at a molar concentration ranging from about 50 mole % to about 75 mole %; zirconium oxide at a molar concentration ranging from about 10 mole % to about 30 mole %; and at least one other component, selected from the group consisting of aluminum oxide, hafnium oxide, scandium oxide, neodymium oxide, niobium oxide, samarium oxide, ytterbium oxide, erbium oxide, cerium oxide, and combinations thereof, at a molar concentration ranging from about 10 mole % to about 30 mole %.

Abstract: A cooling system includes a first section of high temperature superconducting (HTS) cable configured to receive a first flow of coolant and to permit the first flow of coolant to flow therethrough. The system may further include a second section of high temperature superconducting (HTS) cable configured to receive a second flow of coolant and to permit the second flow of coolant to flow therethrough. The system may further include a cable joint configured to couple the first section of HTS cable and the second section of HTS cable. The cable joint may be in fluid communication with at least one refrigeration module and may include at least one conduit configured to permit a third flow of coolant between said cable joint and said at least one refrigeration module through a coolant line separate from said first and second sections of HTS cable. Other embodiments and implementations are also within the scope of the present disclosure.

Abstract: A fastening device is provided for fastening at least one article on a carrier. The fastening device includes at least one positioning component, a fixed plate fixed on the carrier, and a pressing plate positioned on the fixed plate by the positioning component. The pressing plate has at least one positioned portion and a retaining plate corresponding to the fixed plate. The retaining plate abuts against a side edge of the article for preventing the article from moving along a first direction. The positioning component movably passes through the positioned portion to allow the pressing plate to selectively move along the first direction and be positioned on the fixed plate for adjusting the distance between the retaining plate and the fixed plate.

Abstract: A method and an apparatus for removing polymer from a substrate are provided. In one embodiment, an apparatus utilized to remove polymer from a substrate includes a processing chamber having a chamber wall and a chamber lid defining a process volume, a substrate support assembly disposed in the processing chamber, and a remote plasma source coupled to the processing chamber through an outlet port formed within the chamber wall, the outlet port having an opening pointing toward an periphery region of a substrate disposed on the substrate support assembly, wherein the remote plasma source is fabricated from a material resistant to hydrogen species.

Abstract: An HTS cable assembly is provided which includes a cryostat or housing, an HTS wire bundle disposed longitudinally within the cryostat, and plural support members disposed between the HTS wire bundle and the cryostat. The support members are elongate, tubular members having resiliency in both the axial and radial directions. The support members are disposed between the HTS wire bundle and the inner surface of the cryostat in an arrangement that maintains and supports the HTS wire bundle in a spaced-apart relationship with respect to the inner surface of the cryostat. In addition, the plural support members are configured to substantially prevent relative movement between the HTS wire bundle and the cryostat.

Abstract: A component cooling system includes a component tank configured to receive a heat-generating device. The component tank is at least partially filled with a subcooled liquid at a first pressure and at a first temperature. A cryogenic system maintains the component tank at essentially the first temperature. The cryogenic system includes a heat exchange system thermally coupled with at least a portion of the component tank. The heat exchange system is at least partially filled with a second saturated liquid at a second pressure and at essentially the first temperature. A cryostat tank is fluidly-coupled with the heat exchange system and allows for pumpless displacement of the second saturated liquid between the heat exchange system and the cryostat tank.

Abstract: Particulate generation has been a problem in semiconductor device processing in highly corrosive plasma environments. The problem is exacerbated when the plasma is a reducing plasma. Empirically produced data has shown that the formation of a plasma spray coated yttrium-comprising ceramic such as yttrium oxide, Y2O3—ZrO2 solid solution, YAG, and YF3 provides a low porosity coating with smooth and compacted surfaces when such ceramics are spray coated from a powder feed having an average effective diameter ranging from about 22 ?m to about 0.1 ?m. These spray-coated materials reduce the generation of particulates in corrosive reducing plasma environments.

Abstract: Methods for forming dual damascene structures in low-k dielectric materials that facilitate reducing photoresist poison issues are provided herein. In some embodiments, such methods may include plasma etching a via through a first mask layer into a low-k dielectric material disposed on a substrate. The first mask layer may then be removed using a process including exposing the first mask layer to a first plasma comprising an oxygen containing gas and at least one of a dilutant gas or a passivation gas, and subsequently exposing the first mask layer to a second plasma comprising an oxygen containing gas and formed using one of either plasma bias power or plasma source power. An anti-reflective coating may then be deposited into the via and atop the low-k dielectric material. A trench may then be plasma etched through a second mask layer formed atop the anti-reflective coating into the low-k dielectric material.

Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

Abstract: Specialty ceramic materials which resist corrosion/erosion under semiconductor processing conditions which employ a corrosive/erosive plasma. The corrosive plasma may be a halogen-containing plasma. The specialty ceramic materials have been modified to provide a controlled electrical resistivity which suppresses plasma arcing potential.

Abstract: A ceramic article which is resistant to erosion by halogen-containing plasmas used in semiconductor processing. The ceramic article includes ceramic which is multi-phased, typically including two phase to three phases. The ceramic is formed from yttrium oxide at a molar concentration ranging from about 50 mole % to about 75 mole %; zirconium oxide at a molar concentration ranging from about 10 mole % to about 30 mole %; and at least one other component, selected from the group consisting of aluminum oxide, hafnium oxide, scandium oxide, neodymium oxide, niobium oxide, samarium oxide, ytterbium oxide, erbium oxide, cerium oxide, and combinations thereof, at a molar concentration ranging from about 10 mole % to about 30 mole %.

Abstract: A ceramic article useful in semiconductor processing, which is resistant to erosion by halogen-containing plasmas. The ceramic article is formed from a combination of yttrium oxide and zirconium oxide. In a first embodiment, the ceramic article includes ceramic which is formed from yttrium oxide at a molar concentration ranging from about 90 mole % to about 70 mole %, and zirconium oxide at a molar concentration ranging from about 10 mole % to about 30 mole %. In a second embodiment, the ceramic article includes ceramic which is formed from zirconium oxide at a molar concentration ranging from about 96 mole % to about 94 mole %, and yttrium oxide at a molar concentration ranging from about 4 mole % to about 6 mole %.

Abstract: A method of fabricating doped quartz component is provided herein. In one embodiment, the doped quartz component is a yttrium doped quartz ring configured to support a substrate. In another embodiment, the doped quartz component is a yttrium and aluminum doped cover ring. In yet another embodiment, the doped quartz component is a yttrium, aluminum and nitrogen containing cover ring.