Abstract: A method of fabricating silicon parts are provided herein. The method includes growing a silicon sample, machining the sample to form a part, and annealing the part by exposing the part sequentially to one or more gases. Process conditions during silicon growth and post-machining anneal are designed to provide silicon parts that are particularly suited for use in corrosive environments.

Abstract: Methods of applying specialty ceramic materials to semiconductor processing apparatus, where the specialty ceramic materials are resistant to halogen-comprising plasmas. The specialty ceramic materials contain at least one yttrium oxide-comprising solid solution. Some embodiments of the specialty ceramic materials have been modified to provide a resistivity which reduces the possibility of arcing within a semiconductor processing chamber.

Abstract: A cryogenically-cooled HTS cable is configured to be included within a utility power grid having a maximum fault current that would occur in the absence of the cryogenically-cooled HTS cable. The cryogenically-cooled HTS cable includes a continuous liquid cryogen coolant path for circulating a liquid cryogen. A continuously flexible arrangement of HTS wires has an impedance characteristic that attenuates the maximum fault current by at least 10%. The continuously flexible arrangement of HTS wires is configured to allow the cryogenically-cooled HTS cable to operate, during the occurrence of a maximum fault condition, with a maximum temperature rise within the HTS wires that is low enough to prevent the formation of gas bubbles within the liquid cryogen.

Abstract: A superconducting transformer system is configured to be included within a utility power grid having a known fault current level. The superconducting transformer system includes a non-superconducting transformer interconnected between a first node and a second node of the utility power grid. A superconducting transformer is interconnected between the first node and the second node of the utility power grid. The superconducting transformer and the non-superconducting transformer are electrically connected in parallel. The superconducting transformer has a lower series impedance than the non-superconducting transformer when the superconducting transformer is operated below a critical current level and a critical temperature. The superconducting transformer is configured to have a series impedance that is at least N times the series impedance of the non-superconducting transformer when the superconducting transformer is operated at or above one or more of the critical current level and the critical temperature.

Abstract: A superconducting electrical cable system is configured to be included within a utility power grid. The superconducting electrical cable system includes a superconducting electrical path interconnected between a first and a second node within the utility power grid. A non-superconducting electrical path is interconnected between the first and second nodes within the utility power grid. The superconducting electrical path and the non-superconducting electrical path are electrically connected in parallel. The superconducting electrical path has a lower series impedance, when operated below a critical current level, than the non-superconducting electrical path. The superconducting electrical path has a higher series impedance, when operated at or above the critical current level, than the non-superconductor electrical path.

Abstract: A cryogenically-cooled HTS wire includes a stabilizer having a total thickness in a range of 200-600 micrometers and a resistivity in a range of 0.8-15.0 microOhm cm at approximately 90 K. A first HTS layer is thermally-coupled to at least a portion of the stabilizer.

Abstract: A superconducting electrical cable system is configured to be included within a utility power grid having a known fault current level. The superconducting electrical cable system includes a non-superconducting electrical path interconnected between a first node and a second node of the utility power grid. A superconducting electrical path is interconnected between the first node and the second node of the utility power grid. The superconducting electrical path and the non-superconducting electrical path are electrically connected in parallel, and the superconducting electrical path has a lower series impedance than the non-superconducting electrical path when the superconducting electrical path is operated below a critical current level and a critical temperature.

Abstract: High-current, compact, flexible conductors containing high temperature superconducting (HTS) tapes and methods for making the same are described. The HTS tapes are arranged into a stack, a plurality of stacks are arranged to form a superstructure, and the superstructure is twisted about the cable axis to obtain a HTS cable. The HTS cables of the invention can be utilized in numerous applications such as cables employed to generate magnetic fields for degaussing and high current electric power transmission or distribution applications.

Abstract: Method and system for retrieving advertisement information. Information characterizing a user's past search behavior is utilized in creating index data that associate individual users to advertisements. When a search request from a user is received, the index data are utilized to identify one or more advertisements with respect to the received user's search request. Such identified advertisements match the user's past search behavior.

Abstract: A method of fabricating yttria parts is provided herein. In one embodiment, the method includes sintering a yttria sample, machining the sintered sample to form a part, and annealing the part by heating the part at a predetermined heating rate, maintaining the part at a constant annealing temperature, and cooling the part at a predetermined cooling rate. At least one of the sintering and annealing atmospheres is an oxygen-containing atmosphere.

Abstract: A method and system for providing protection for a superconducting electrical cable located in a utility power network includes detecting a fault current on the superconducting electric cable, determining the cumulative total energy dissipated in the superconducting electrical cable from the fault current and at least one prior fault current over a predetermined time period, and determining whether to disconnect the superconducting electrical cable from the utility power network on the basis of the cumulative total energy dissipated.

Abstract: A method and system for providing protection for a superconducting electrical cable located in a utility power network includes detecting a fault current on the superconducting electric cable, determining the cumulative total energy dissipated in the superconducting electrical cable from the fault current and at least one prior fault current over a predetermined time period, and determining whether to disconnect the superconducting electrical cable from the utility power network on the basis of the cumulative total energy dissipated.

Abstract: A cortical column emulation circuit includes a capacitor which is coupled at a first end to a source of reference potential by a switch, a current source coupled to the first end of the capacitor for charging the capacitor when the switch is open to develop a capacitor voltage between the first end and the second end of the capacitor; and a comparator which compares the voltage across the capacitor to a threshold potential and generates a pulse signal when the capacitor voltage is greater than the threshold voltage. The pulse signal closes the switch to connect the first end of the capacitor to the source of reference potential. A set of cortical column emulation circuits may be coupled together by an adaptive coupling to form a cortical region emulation circuit. The adaptive coupling circuit weights an input stimulus and a plurality of state vector elements by variable coupling coefficients.

Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

Abstract: Method, materials and structures are described for the fabrication of dual damascene features in integrated circuits. In via-first dual damascene fabrication, a bottom-antireflective-coating (“BARC”) is commonly deposited into the via and field regions surrounding the via, 107. Subsequent trench etch with conventional etching chemistries typically results in isolated regions of BARC, 107a, surrounded by “fencing” material, 108, at the bottom of the via. Such fencing hinders conformal coating with barrier/adhesion layers and can reduce device yield. The present invention relates to the formation of a BARC plug, 107c, partially filling the via and having a convex upper surface, 400, prior to etching the trench. Such a BARC structure is shown to lead to etching without the formation of fencing and a clean dual damascene structure for subsequent coating.

Abstract: A method for dealing with process specific physical effects applies dimensional modifications to an IC layout to compensate for performance variations caused by the physical effects. Because the dimensional modifications harmonize the performance of the actual IC with the performance of the IC model, time-consuming re-verification operations are not required. Current drive variations caused by shallow trench isolation (STI) stress can be compensated for by adjusting the gate dimensions of the affected transistors to increase or decrease current drive as necessary. Such physical effect compensation can be applied before, after, or even concurrently with optical proximity correction (OPC). The dimensional modifications for physical effect compensation can also be incorporated into an OPC engine.

Abstract: A method for etching a metal layer formed on a substrate to form a metal line, using an amorphous carbon layer as a pattern mask. One embodiment of the method of the invention etches a metal layer formed on a substrate, for forming a metal line, by depositing an amorphous carbon layer on the metal layer, patterning the amorphous carbon layer to provide a pattern mask on the metal layer, thus exposing portions of said metal layer; and etching the exposed portions of the metal layer, to form a metal line. In an embodiment, the metal layer comprises a copper layer.

Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

Abstract: A method is provided for etching a dielectric structure. The dielectric structure comprises: (a) a layer of undoped silicon oxide or F-doped silicon oxide; and (b) a layer of C,H-doped silicon oxide. The dielectric structure is etched in a plasma-etching step, which plasma-etching step is conducted using a plasma source gas that comprises nitrogen atoms and fluorine atoms. As one example, the plasma source gas can comprise a gaseous species that comprises one or more nitrogen atoms and one or more fluorine atoms (e.g., NF3). As another example, the plasma source gas can comprise (a) a gaseous species that comprises one or more nitrogen atoms (e.g., N2) and (b) a gaseous species that comprises one or more fluorine atoms (e.g., a fluorocarbon gas such as CF4). In this etching step, the layer of C,H-doped silicon oxide is preferentially etched relative to the layer of undoped silicon oxide or F-doped silicon oxide. The method of the present invention is applicable, for example, to dual damascene structures.