Abstract: A cathode active material for a lithium secondary battery includes a lithium metal oxide particle and a thio-based compound formed on at least portion of a surface of the lithium metal oxide particle. The thio-based compound has a double bond that contains a sulfur atom. Chemical stability of the lithium metal oxide particle may be improved and surface residues may be reduced by the thio-based compound.

Abstract: An apparatus and method for manufacturing iron-based mixed powder with excellent flowability is provided. The apparatus includes a hopper which stores and discharges a main raw material of iron-based powder, a transport means which transports the main raw material of iron-based powder discharged from the hopper, a magnetizing means that applies magnetic force to the main raw material transported and falling from the transport means to process the main raw material of iron-based powder into a main raw material bundle in a crumbly type in which the main raw material of iron-based powder is agglomerated with each other, a first mixer in which the main raw material bundle in a magnetized state and an auxiliary raw material of iron-based powder are loaded and mixed while being rotated and transported, and a second mixer in which a first iron-based mixed powder is mixed while being rotated and transported.

Abstract: The present invention relates to a method and device for manufacturing artificial marble. According to the present invention, artificial marble having a stripe pattern similar to that of natural stone, such as striato, may be provided.

Abstract: The present invention relates to a method and device for manufacturing artificial marble. According to the present invention, artificial marble having a stripe pattern similar to that of natural stone, such as striato, may be provided.

Abstract: The present application relates to a pattern forming method for quartz surface and a pattern forming device for quartz surface. According to the pattern forming method for quartz surface of the present application, by comprising a step of forming a pattern and a step of forming a color, it is possible to freely express the color on the pattern simultaneously along with forming the pattern on the quartz surface. And, in addition to these steps, by optionally comprising a step of additionally forming a pattern, it is possible to freely form a desired pattern on the quartz surface, and, by adding long line type patterns on the quartz surface unlike existing conventional quartz surfaces, it is possible to produce the quartz surface showing patterns and textures which are more natural and close to natural stone.

Abstract: The present invention relates to a method and device for manufacturing artificial marble. According to the present invention, artificial marble having a stripe pattern similar to that of natural stone, such as striato, may be provided.

Abstract: The present application relates to a pattern forming method for quartz surface and a pattern forming device for quartz surface. According to the pattern forming method for quartz surface of the present application, by comprising a step of forming a pattern and a step of forming a color, it is possible to freely express the color on the pattern simultaneously along with forming the pattern on the quartz surface. And, in addition to these steps, by optionally comprising a step of additionally forming a pattern, it is possible to freely form a desired pattern on the quartz surface, and, by adding long line type patterns on the quartz surface unlike existing conventional quartz surfaces, it is possible to produce the quartz surface showing patterns and textures which are more natural and close to natural stone.

Abstract: A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.

Abstract: A dynamic random access memory (DRAM) includes a memory cell array, a data input/output circuit, and a data randomizer configured to randomize data to be stored in the memory cell array. The data randomizer includes an encoder configured to generate write data by encoding input data received from the data input/output circuit using a randomization code and to output the write data to the memory cell array. The data randomizer further includes a decoder configured to generate output data by decoding read data received from the memory cell array using the randomization code and to output the output data to the data input/output circuit.

Abstract: A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.

Abstract: A semiconductor memory device is provided. The semiconductor memory device supplies to a sense amplifier a first voltage and a second voltage during data sensing, so that data sensing margin and a data sensing speed increase.

Abstract: A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.

Abstract: A bitline sense amplifier includes a pre-sensing unit and an amplification unit. The pre-sensing unit is connected to a first bitline and a second bitline, and is configured to perform a pre-sensing operation by controlling a voltage level of the second bitline based on at least one pre-sensing voltage and variation of a voltage level of the first bitline. The amplification unit is configured to perform a main amplification operation by amplifying a pre-sensed voltage difference based on a first voltage signal and a second voltage signal. The pre-sensed voltage difference indicates a difference between the voltage level of the first bitline and the voltage level of the second bitline after the pre-sensing operation.

Abstract: A semiconductor memory device includes a first memory block, a second memory block, and a signal controller. The first memory block is configured to generate a first blocking signal, a second blocking signal, and a first enable signal in response to a row address, and to block and enable wordlines of the memory block in response to the first blocking signal and the first enable signal, respectively. The second memory block is configured to generate a third blocking signal, a fourth blocking signal, and a second enable signal in response to the row address, and to block and enable wordlines of the second memory block in response to the third blocking signal and the second enable signal, respectively. The signal controller is connected between the first memory block and the second memory block and is configured to enable the third blocking signal when the second blocking signal is enabled, and to enable the first blocking signal when the fourth blocking signal is enabled.

Abstract: A bitline sense amplifier includes a pre-sensing unit and an amplification unit. The pre-sensing unit is connected to a first bitline and a second bitline, and is configured to perform a pre-sensing operation by controlling a voltage level of the second bitline based on at least one pre-sensing voltage and variation of a voltage level of the first bitline. The amplification unit is configured to perform a main amplification operation by amplifying a pre-sensed voltage difference based on a first voltage signal and a second voltage signal. The pre-sensed voltage difference indicates a difference between the voltage level of the first bitline and the voltage level of the second bitline after the pre-sensing operation.

Abstract: A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.

Abstract: A semiconductor memory device includes a memory cell array block including a plurality of memory cells each connected to one of a plurality of bit lines and one of a plurality of word lines, a sense amplifier connected to a half of the plurality of bit lines, the sense amplifier for sensing and amplifying a voltage between each of the half of the bit lines and a corresponding complementary bit line; and a dummy block connected to the half of the plurality of bit lines of the memory cell array block, the dummy block for controlling a load on the memory cell array block to be different from a load on the dummy block according to a dummy load signal.

Abstract: A semiconductor memory device is provided. The semiconductor memory device supplies to a sense amplifier a first voltage and a second voltage during data sensing, so that data sensing margin and a data sensing speed increase.

Abstract: A semiconductor memory device includes a first memory block, a second memory block, and a signal controller. The first memory block is configured to generate a first blocking signal, a second blocking signal, and a first enable signal in response to a row address, and to block and enable wordlines of the memory block in response to the first blocking signal and the first enable signal, respectively. The second memory block is configured to generate a third blocking signal, a fourth blocking signal, and a second enable signal in response to the row address, and to block and enable wordlines of the second memory block in response to the third blocking signal and the second enable signal, respectively. The signal controller is connected between the first memory block and the second memory block and is configured to enable the third blocking signal when the second blocking signal is enabled, and to enable the first blocking signal when the fourth blocking signal is enabled.

Abstract: Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data as versions of the first and second ordered groups of data in parallel at outputs thereof whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.