Abstract: A semiconductor memory device having a write masking function and a write masking method are provided. The semiconductor memory device includes a plurality of write bit lines, a plurality of write word lines, a plurality of write drivers, a plurality of MOS transistors, a plurality of latch circuits, and a plurality of precharge controllers. Each of the write drivers receives input data, a write enable signal and a write masking signal, outputs the input data when the write enable signal is activated and the write masking signal is deactivated, and does not output the input data when the write masking signal is activated. Each of the latch circuits includes an inverter having a large driving capacity and an inverter having a small driving capacity. When a precharge signal is activated, each of the precharge controllers precharges a corresponding write bit line to the logic threshold voltage of the inverter having the large driving capacity.

Abstract: A redundancy circuit of a semiconductor memory device includes a mode setting circuit that generates mode signal, an input selecting circuit that generates selecting signal in response to the mode signals, and a decoding circuit that, in response to the mode selecting signals, generates decoding signals. The redundancy mode signals include a bank redundancy mode signal, an array redundancy mode signal, and a column address group redundancy mode signal. The selecting signal identifies a bank in bank redundancy mode, an array in an array redundancy mode, and a column address group in column address group redundancy mode. The decoding signals initiate a replacement of a data I/O line pair associated to a defective memory cell in the semiconductor memory device. A redundancy method includes: generating the redundancy mode signals; generating the selecting signal in response to the redundancy mode signals; and generating the decoding signals.

Abstract: A precharging apparatus and method is applicable to a semiconductor device having a stack bank-type structure.

Abstract: An MML integrated circuit device includes a memory block, a logic circuit and a buffer memory, and a selection circuit that is coupled between the logic circuit and the buffer memory. The first selection portion is responsive to external data and to the logic circuit, to transmit external data or data from the logic circuit to the memory block via the buffer memory. Thus, MML integrated circuit devices can use the buffer memory to access the memory block during a normal operational mode and during a test mode. MML integrated circuit devices also preferably include a data expansion portion that is coupled between the external data and the selection portion, to replicate the external data a predetermined number of times and to transmit the replicated external data to the selection portion.

Abstract: Integrated circuit memory devices having merged data test capability include first and second memory cell arrays in first and second blocks of memory, respectively, a first global input/output line and switches for enabling transfer of data from the first memory cell array to the first global input/output line in response to a first merged data test control signal P1 and enabling transfer of data from the second memory cell array to the first global input/output line in response to a second merged data test control signal P2. A highly integrated merged data test circuit is also provided with test cells therein and each test cell is capable of testing multiple memory cell arrays in at least two blocks of memory. A first merged data test circuit is provided which has a first input electrically coupled to the first global input/output line and a first output which generates first and second error signals upon detection of a failure in the first and second memory cell arrays, respectively.

Abstract: An integrated circuit having a wide internal data path, such as a Merged Memory and Logic (MML) integrated circuit, is tested by serially comparing data on one of the data paths to data on selected others of the data paths. A first indication is provided if the serially compared data on the one of the data paths and on the selected others of the data paths are all a first logic value. A second indication is provided if the serially compared data on the one of the data paths and on the selected others of the data paths are all a second logic value. A third indication is provided if the serially compared data on the one of the data paths and on the selected others of the data paths are of differing logic values. By serially comparing data on one of the data paths to data on selected others of the data paths, a reduced number of comparators may be provided. Efficient circuits and methods for testing integrated circuits, such as memory integrated circuits or logic integrated circuits, may thereby be provided.