Abstract: A capacitor component includes a body including a dielectric layer and first and second internal electrode layers, and external electrodes disposed on the body and connected to the first and second internal electrode layers, respectively. The body includes an active portion in which the first and second internal electrode layers are alternately disposed with the dielectric layer interposed therebetween, a cover portion disposed on an upper portion and a lower portion of the active portion, and a side margin portion disposed on both sides of the active portion opposing each other. When a content of magnesium (Mg) included in the active portion is A1, a content of magnesium (Mg) included in the cover portion is C1, and a content of magnesium (Mg) included in the margin portion is M1, 0<A1<M1?C1 and A1/C1?0.60 are satisfied.

Abstract: The present disclosure relates to a printed circuit board including, a first insulating layer, a first metal layer disposed on the first insulating layer, a bridge disposed on the first metal layer and including a bridge insulating layer and a bridge circuit layer, a second insulating layer disposed on the first insulating layer and covering at least a portion of the bridge, a second metal layer disposed on the second insulating layer, and a connecting via penetrating the bridge and the second insulating layer to connect the first metal layer to the second insulating layer. The connecting via is spaced apart from the bridge circuit layer.

Abstract: A semiconductor memory device comprises a substrate including a first source/drain region and a second source/drain region, a trench between the first source/drain region and the second source/drain region and formed in the substrate, a cell gate insulating layer on sidewalls and a bottom surface of the trench, a cell gate electrode on the cell gate insulating layer, a work function control pattern on the cell gate electrode, including N-type impurities and a cell gate capping pattern on the work function control pattern. The work function control pattern includes a semiconductor material. The work function control pattern includes a first region and a second region between the first region and the cell gate electrode. A concentration of the N-type impurities in the first region is greater than a concentration of the N-type impurities in the second region.

Abstract: Disclosed herein are a decoding method and apparatus and an encoding method and apparatus for deriving an intra-prediction mode. An intra-prediction mode may be derived using a method for deriving an intra-prediction mode based on a neighbor block of the target block, a method for deriving an intra-prediction mode using signaling of the intra-prediction mode of the target block, or a method for deriving an adaptive intra-prediction mode based on the type of a target slice. An MPM list may be used to derive the intra-prediction mode, and a temporal neighbor block or the like may be used to configure the MPM list.

Abstract: A semiconductor memory device is provided. The semiconductor memory device comprises a substrate including a cell region having an active region defined by a cell element isolation layer, a peripheral region near the cell region, and a boundary region between the cell region and the peripheral region. The device includes a word line structure in the substrate and extending in a first direction, a bit line structure on the substrate extending from the cell region to the boundary region in a second direction that crosses the first direction, including first and second cell conductive layers sequentially stacked on the substrate, and a bit line contact between the substrate and the bit line structure and connecting the substrate with the bit line structure. The second cell conductive layer in the boundary region is thicker than the second cell conductive layer in the cell region.

Abstract: Disclosed herein are a decoding method and apparatus and an encoding method and apparatus that perform inter-prediction using a motion vector predictor. For a candidate block in a col picture, a scaled motion vector is generated based on a motion vector of the candidate block. When the scaled motion vector indicates a target block, a motion vector predictor of the target block is generated based on the motion vector of the candidate block. The motion vector predictor is used to derive the motion vector of the target block in a specific inter-prediction mode such as a merge mode and an AMVP mode.

Abstract: A display device comprises a display panel including a plurality of sub-pixels defined by a plurality of gate lines and a plurality of data lines; and an auxiliary ground voltage line disposed between two adjacent data lines of the plurality of data lines.

Abstract: An image encoding/decoding method is provided. An image decoding method of the present invention may comprise deriving an intra-prediction mode of a current luma block, deriving an intra-prediction mode of a current chroma block based on the intra-prediction mode of the current luma block, generating a prediction block of the current chroma block based on the intra-prediction mode of the current chroma block, and the deriving of an intra-prediction mode of a current chroma block may comprise determining whether or not CCLM (Cross-Component Linear Mode) can be performed for the current chroma block.

Abstract: An apparatus for providing brain lesion information based on an image includes a magnetic resonance angiography (MRA) provider configured to provide an environment capable of displaying 3D time-of-flight magnetic resonance angiography (3D TOF MRA) using user input, a brain lesion input unit configured to generate and manage a brain lesion image, a maximum intensity projection (MIP) converter configured to configure MIP image data including at least one image frame corresponding to a projection position of the brain lesion image, a noise remover configured to remove noise of brain lesion information and to configure corrected MIP image data, from which the noise is removed, and an MRA reconfiguration unit configured to reconfigure a corrected brain lesion image by back-projecting the corrected MIP image data.

Abstract: The present invention relates to a composition for etching, comprising a first inorganic acid, a first additive represented by Chemical Formula 1, and a solvent. The composition for etching is a high-selectivity composition that can selectively remove a nitride film while minimizing the etch rate of an oxide film, and which does not have problems such as particle generation, which adversely affect the device characteristics.

Abstract: A printed circuit board includes a substrate, a first pad and a second pad, respectively disposed on an upper side of the substrate, a first socket disposed in the substrate and including a first circuit, and a first trace disposed in the substrate and disposed between the first and second pads and the first socket with respect to a lamination direction. At least a portion of the first circuit is electrically connected to each of the first and second pads, and is electrically connected to the second pad through a path passing through the first trace.

Abstract: A printed circuit board includes: a first insulating material; and a second insulating material disposed on one surface of the first insulating material, and including first and second cavities having depths different from each other. At least one groove portion is disposed in a side surface of each of the first and second cavities.

Abstract: A printed circuit board includes: a bridge including a first insulating material, a wiring pattern disposed in the first insulating layer, a metal post disposed on the first insulating material and connected to the wiring pattern, and a second insulating material disposed on the first insulating material and covering at least a portion of the metal post; a first build-up insulating material disposed around the bridge; and a first redistribution pattern disposed on the second insulating material and the first build-up insulating material and including a metal pad connected to the metal post.

Abstract: A printed circuit board includes: a first insulating layer; a via pad including a first layer embedded in the first insulating layer and a second layer disposed on the first layer; and a first via layer disposed on the via pad, wherein the second layer has a width decreasing in a direction away from the first layer in a stacking direction of the first and second layers.

Abstract: A printed circuit board includes: a first insulating layer including a first cavity and a second cavity; a first electronic component disposed in the first cavity and including a first pad disposed in a first surface direction of the first insulating layer; a second electronic component disposed in the second cavity and including a second pad disposed in a second surface direction, facing the first surface direction, of the first insulating layer; a second insulating layer disposed on each of first and second surfaces of the first insulating layer and in the first cavity to cover the first electronic component; and a third insulating layer disposed on the first surface of the first insulating layer and in the second cavity to cover the second electronic component.

Abstract: A method of etching a metal barrier layer and a metal layer is provided. The method includes forming the metal barrier layer and the metal layer on a substrate, and using an etching composition to etch the metal barrier layer and the metal layer. The etching composition may include an oxidant selected from nitric acid, bromic acid, iodic acid, perchloric acid, perbromic acid, periodic acid, sulfuric acid, methane sulfonic acid, p-toluenesulfonic acid, benzenesulfonic acid, or a combination thereof, a metal etching inhibitor including a compound expressed by Chemical Formula 1, and a metal oxide solubilizer selected from phosphoric acid, phosphate, carboxylic acid having 3 to 20 carbon atoms, or a combination thereof.

Abstract: A printed circuit board includes a first insulating layer; a first wiring layer disposed on one surface of the first insulating layer and including a pad; a second insulating layer disposed on the one surface of the first insulating layer and covering the first wiring layer; a second wiring layer disposed on one surface of the second insulating layer and including a metal pattern; a third insulating layer disposed on the one surface of the second insulating layer and covering the second wiring layer; and a cavity extending through each of the second and third insulating layers, and having a bottom surface and a sidewall respectively exposing the pad of the first wiring layer and the metal pattern of the second wiring layer. The cavity includes a non-through groove in the one surface of the first insulating layer.

Abstract: A display device comprises a display panel including a plurality of sub-pixels defined by a plurality of gate lines and a plurality of data lines; and an auxiliary ground voltage line disposed between two adjacent data lines of the plurality of data lines.

Abstract: A printed circuit board includes: a wiring substrate including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers; and a bridge embedded in the wiring substrate and having a plurality of connection pads thereon. An uppermost wiring layer of the plurality of wiring layers includes a plurality of bump pads connected to the plurality of connection pads, and a pitch between at least two adjacent connection pads of the plurality of connection pads is larger than a pitch between at least two adjacent ones of the plurality of bump pads.

Abstract: A printed circuit board includes: an insulating member; a first wiring layer disposed in the insulating member, and including first and second pattern layers spaced apart from each other based on a thickness direction of the printed circuit board; and a second wiring layer disposed in the insulating member, and spaced apart from the first pattern layer over the first pattern layer based on the thickness direction. Based on the thickness direction, an insulation distance between the first pattern layer and the second pattern layer is smaller than an insulation distance between the first pattern layer and the second wiring layer, and each of the first and second pattern layers is thinner than the second wiring layer.