Abstract: The present disclosure is directed to nanocomposites comprising a co-sintered composition of a MXene crystal form composition and an inorganic oxide, or oxide-type ceramic and methods of making and using the same.

Abstract: Embodiments of this application provide an upload interface identification method performed at an identification server. The identification server obtains a to-be-identified request packet that is contained in request packets from a page client to a page server. After parsing a content feature of the to-be-identified request packet, the server determines whether the content feature corresponds to a predefined content feature of an upload request packet authorized by the page server. The server then determines that an interface address indicated by the upload request packet corresponds to an upload interface of the to-be-identified request packet if the content feature corresponds to the set content feature of the upload request packet.

Abstract: An edible pet chew incorporates a chewy sheet member and a plant based meat analogue member being assembled together. The meat analogue member imitates an appearance and texture of meat jerky and may have an internal aligned fibrous structure. In another aspect of the present invention, the edible pet chew is a rawhide munchy product including a plurality of rawhide bits, a plurality of meat analogue tiny chunks and a binder. In yet another aspect of the present invention, the edible pet chew includes a plant based extruded or injection-formed chewy piece member and a meat analogue member, and the meat analogue member wraps about the chewy piece member.

Abstract: A method includes depositing a resist layer onto a hard mask layer to form a multi-layer patterning material film stack on a semiconductor substrate, directing patterning radiation onto the film stack to form a developed pattern in the resist layer and exposing the film stack to at least one gas precursor in connection with a sequential infiltration synthesis process. The film stack is configured to facilitate selective infiltration of the at least one gas precursor into the resist layer.

Abstract: A method of forming cut conductive lines is provided. The method includes forming a trough in a dielectric cover layer over a plurality of electrical contacts. The method further includes filling the trough with a planarization layer, and forming a plurality of vias in the planarization layer and the dielectric cover layer, wherein each of the plurality of vias is aligned with one of the plurality of electrical contacts. The method further includes removing the planarization layer, and forming a sacrificial via plug in each of the plurality of vias in the dielectric cover layer. The method further includes forming a fill layer in the trough, and forming a planarization layer opening through the fill layer, wherein the planarization layer opening is positioned between two adjacent sacrificial via plugs. The method further includes forming a separator in the planarization layer opening.

Abstract: Burst throttling methods may be used to manage computing resources of a data storage service. Tokens may represent I/O operations executed by a customer of the data storage service. A first token bucket may contain a set of tokens representing the overall I/O operation capacity of the data storage service. Additionally, a second token bucket may contain a set of tokens for a given logical volume maintained by the data storage service. When I/O requests are received tokens may be charged the first token bucket and the second token bucket. Furthermore, if there is sufficient capacity, the data storage service may charge a reduced number of tokens to the third token bucket.

Abstract: A method for fabricating a semiconductor device includes forming at least one sacrificial via within at least one self-aligned via hole of a base structure, forming a region having a misalignment relative to the at least one sacrificial via by cut patterning, and forming a cut cavity having a geometry for minimizing effects of the misalignment by protecting at least one self-aligned via due to the misalignment.

Abstract: A layer structure for a photovoltaic device comprising: a transparent conductive oxide layer comprising indium tin oxide (20); a layer of tin dioxide (30) adjacent to the indium tin oxide of the transparent conductive oxide layer; and a layer of zinc magnesium oxide (40) adjacent to the layer of tin dioxide, wherein the layer of zinc magnesium oxide is an alloy of zinc oxide and magnesium oxide. A photovoltaic device comprising: a transparent conductive oxide layer comprising indium tin oxide; a layer of tin dioxide disposed on the indium tin oxide of the transparent conductive oxide layer; a layer of zinc magnesium oxide adjacent to the layer of tin dioxide, wherein the layer of zinc magnesium oxide is an alloy of zinc oxide and magnesium oxide; and an absorber layer disposed on the layer of zinc magnesium oxide, wherein the absorber layer comprises cadmium, tellurium, selenium, or any combination thereof.

Abstract: A method, system, and computer program product for obtaining a candidate event sequence that includes at least one event for achieving a goal, obtaining a reference event sequence, the candidate event sequence comprising at least one event that is not comprised in the reference event sequence, comparing an effectiveness of the candidate event sequence on the goal and an effectiveness of the reference event sequence on the goal, and identifying the candidate event sequence as an effective sequence for achieving the goal in response to the effectiveness of the candidate event sequence being better than the effectiveness of the reference event sequence.

Abstract: Cold sintering of materials includes using a process of combining at least one inorganic compound, e.g., ceramic, in particle form with a solvent that can partially solubilize the inorganic compound to form a mixture; and applying pressure and a low temperature to the mixture to evaporate the solvent and densify the at least one inorganic compound to form sintered materials.

Abstract: An adaptive pulse width modulation threshold is provided for a flyback converter that controls the transition between the pulse frequency mode of operation and the pulse width modulation mode of operation. The adaptive pulse width modulation mode is adapted responsive to an output voltage for the flyback converter.

Abstract: A method of making an adhesion layer of an extreme ultraviolet (EUV) stack is presented. The method includes grafting an ultraviolet (UV) sensitive polymer brush on a hardmask, the polymer brush including a UV cleavable unit, depositing EUV resist over the polymer brush, exposing the EUV resist to remove the EUV resist in exposed areas by applying a developer, and flooding the exposed area with a UV light and a solvent developer to remove exposed portions of the polymer brush.

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least a first channel region and a second channel region. The first channel region and the second channel region each include metal gate structures surrounding a different nanosheet channel layer. The metal gate structures of the first and second channel regions are respectively separated from each other by an unfilled gap. The method includes forming a gap fill layer between and in contact with gate structures surrounding nanosheet channel layers in multiple channel regions. Then, after the gap fill layer has been formed for each nanosheet stack, a masking layer is formed over the gate structures and the gap fill layer in at least a first channel region. The gate structures and the gap fill layer in at least a second channel region remain exposed.

Abstract: Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.

Abstract: Cold sintering of materials includes using a process of combining at least one inorganic compound, e.g., ceramic, in particle form with a solvent that can partially solubilize the inorganic compound to form a mixture; and applying pressure and a low temperature to the mixture to evaporate the solvent and densify the at least one inorganic compound to form sintered materials.

Abstract: Various examples disclosed relate to a substrate. The substrate includes a cold-sintered hybrid material. The cold-sintered hybrid material includes a polymer component and a ceramic component. The substrate further includes a conductor at least partially embedded within the cold-sintered hybrid material. The substrate further includes a via attached to the conductor. The cold-sintered hybrid material has a relative density in a range of from about 80% to about 99%.

Abstract: Provided are a PCR primer pair and an application thereof. The PCR primer pair comprises a first primer and a second primer, wherein the first primer comprises a first specific sequence, a first random sequence, and a first universal sequence, the first specific sequence is located at the 3? end of the first primer, the first random sequence is located at the 5? end of the first primer, and the first universal sequence is located between the first specific sequence and the first random sequence; the second primer comprises a second specific sequence, a second random sequence, and a second universal sequence, the second specific sequence is located at the 3? end of the second primer, the second random sequence is located at the 5? end of the second primer, and the second universal sequence is located between the second specific sequence and the second random sequence, wherein the first random sequence and the second random sequence are inversely complementary.

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least a first channel region and a second channel region. The first channel region and the second channel region each include metal gate structures surrounding a different nanosheet channel layer. The metal gate structures of the first and second channel regions are respectively separated from each other by an unfilled gap. The method includes forming a gap fill layer between and in contact with gate structures surrounding nanosheet channel layers in multiple channel regions. Then, after the gap fill layer has been formed for each nanosheet stack, a masking layer is formed over the gate structures and the gap fill layer in at least a first channel region. The gate structures and the gap fill layer in at least a second channel region remain exposed.

Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate. Forming the patterning material film stack more particularly includes forming a hard mask layer and forming a resist layer over the hard mask layer. The hard mask layer is configured to support selective deposition of a metal-containing layer on the resist layer, the selective deposition of the metal-containing layer on the resist layer occurring after pattern development. The method further includes exposing the multi-layer patterning material film stack to patterning radiation to form a desired pattern in the resist layer, developing the pattern formed in the resist layer, and selectively depositing the metal-containing layer on the developed pattern in the resist layer. The selective deposition avoids deposition of the metal-containing layer on portions of the hard mask layer corresponding to respective openings in the resist layer.

Abstract: An adhesion promoter composition comprising at least one of the following compounds: (a) a cyclic compound having the formula: (b) a non-cyclic compound having the formula: wherein R1 and R2 each independently represents a non-photoactive phenyl, a photoactive phenyl or a C1-C4 alkyl; R3 represents a non-photoactive phenyl; R4 represents a photoactive phenyl; W represents Si or Ge; n represents an integer of value greater than 1; m represents an integer between 0 and 1.