Abstract: Mechanisms are provided for determining an event rate. The mechanisms sample a sequence of events to generate a set of sampled events. At least a subset of the sampled events have associated event sequence values indicating a position of the sampled event within the sequence of events. The mechanisms group the sampled events into a plurality of event groups based on a common characteristic of the events. The mechanisms determine, for each event group, sequence values of sampled events associated with the event group. The mechanisms calculate, for each event group, an estimated event rate based on the sequence values of the sampled events associated with the event group and the total number of events in the sequence of events.

Abstract: Mechanisms are provided for analyzing data traffic through a network. The mechanisms sample data packets of a data flow through a normal port of a network forwarding device of the network. The sampling is performed at least by configuring the network forwarding device to implement port mirroring of the normal port to a designated mirror port of the network forwarding device. The mechanisms forward sampled data packets, copied to the mirror port by virtue of the port mirroring, to a collector computing device. The mechanisms process, by the collector computing device, the sampled data packets to analyze the data flow through the normal port of the network forwarding device. The mechanisms perform, by the collector computing device, an operation based on results of the analysis.

Abstract: Mechanisms are provided for configuring a data flow between a source device and a destination device in a network. The mechanisms receive, from a network control application, a request to establish a network configuration corresponding to a data flow between the source device and the destination device. The request comprises a fine grained header field tuple for defining the data flow. The mechanisms allocate, from a shadow address pool, a shadow address to be mapped to the fine grained header field tuple. The shadow address pool comprises addresses not being used by devices coupled to the network. The mechanisms configure a network infrastructure of the network to route data packets of the data flow from the source device to the destination device based on the shadow address.

Abstract: Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.

Abstract: Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.

Abstract: According to one aspect of the present disclosure a method and technique for monitoring memory access is disclosed. The method includes monitoring access to a memory unit, updating an activity cache associated with an incrementor with access data corresponding to accesses to the memory unit, monitoring a rate of access to the memory unit, adjusting a sample rate of the access data for storage in the memory unit based on the rate of access, and scaling a value of the access data based on the sample rate.

Abstract: Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.

Abstract: A token value is maintained based on an allowable number of low power transitions of a hard disk drive without adversely affecting reliability, compared to an actual number of low power transitions of said hard disk drive. The allowable number of low power transitions increases over the hard disk drive's lifetime. Before the hard disk drive performs a low power transition, the token is evaluated to determine if the hard disk drive is allowed to perform a low power transition. Low power transitions discussed include parking the head and spinning-down the hard disk drive.

Abstract: An aspect includes deadlock-free routing on arbitrary network topologies using edge-disjoint sub-networks. A network topology of a network is identified. The network includes a plurality of links between a plurality of switches. Each of the links is identified as an edge. A plurality of edge-disjoint sub-networks is constructed from the network topology of the network by routing configuration logic. The plurality of edge-disjoint sub-networks is formed by edges between the switches such that the edges are disjoint relative to each of the edge-disjoint sub-networks. The switches are configured to route traffic on the network with each route staying entirely within one of the plurality of edge-disjoint sub-networks within the network.

Abstract: A mechanism is provided for implementing a per-address spanning tree (PAST) to direct the forwarding of packets in a set of switches. The per-address spanning tree is computed for each identified address in a set of addresses thereby forming a set of per-address spanning trees. A set of forwarding rules associated with each per-address spanning tree in the set of per-address spanning trees is generated and installed all appropriate switches in the set of switches for which the per-address spanning tree is generated so that each switch in the set of switches will forward packets based on the set of forwarding rules installed in that switch.

Abstract: A token value is maintained based on an allowable number of low power transitions of a hard disk drive without adversely affecting reliability, compared to an actual number of low power transitions of said hard disk drive. The allowable number of low power transitions increases over the hard disk drive's lifetime. Before the hard disk drive performs a low power transition, the token is evaluated to determine if the hard disk drive is allowed to perform a low power transition. Low power transitions discussed include parking the head and spinning-down the hard disk drive.

Abstract: A technique for performing storage power management on storage subsystems includes measuring, using a power measurement device, power consumption of a storage subsystem. A first average power and a second average power for the storage subsystem are calculated based on the measured power consumption. In this case, the first average power is calculated over a shorter time period than the second average power. One or more first actuators are incremented in response to the first average power of the storage subsystem being greater than a first power level to reduce the first average power of the storage subsystem below the first power level within a first time period. One or more second actuators are incremented in response to the second average power of the storage subsystem being greater than a second power level and less than the first power level to reduce the second average power of the storage subsystem below the second power level within a second time period that is greater than the first time period.

Abstract: Mechanisms are provided for processing an instruction in a processor of a data processing system. The mechanisms operate to receive, in a processor of the data processing system, an instruction, the instruction including power/performance tradeoff information associated with the instruction. The mechanisms further operate to determine power/performance tradeoff priorities or criteria, specifying whether power conservation or performance is prioritized with regard to execution of the instruction, based on the power/performance tradeoff information. Moreover, the mechanisms process the instruction in accordance with the power/performance tradeoff priorities or criteria identified based on the power/performance tradeoff information of the instruction.

Abstract: A performance control technique for a processing system that includes one or more adaptively-clocked processor cores provides improved performance/power characteristics. An outer feedback loop adjusts the power supply voltage(s) provided to the power supply voltage domain(s) powering the core(s), which may be on a per-core basis or include multiple cores per voltage domain. The outer feedback loop operates to ensure that each core is meeting specified performance, while the cores also include an inner feedback loop that adjusts their processor clock or other performance control mechanism to maximize performance under present operating conditions and within a margin of safety. The performance of each core is measured and compared to a target performance. If the target performance is not met for each core in a voltage domain, the voltage is raised for the voltage domain until all cores meet the target performance.

Abstract: Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.

Abstract: Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.

Abstract: A mechanism is provided for minimizing system power in a data processing system. A management control unit determines whether a convergence has been reached in the data processing system. If convergence fails to be reached, the management control unit determines whether a maximum fan flag is set to indicate that a fan is operating at a maximum speed. Responsive to the maximum fan flag failing to be set, a thermal threshold of the data processing system is either increased or decreased and thereby a fan speed of the data processing system is either increased or decreased based on whether the system power of the data processing system has either increased or decreased and based on whether a temperature of the data processing system has either increased or decreased. Thus, a new thermal threshold and a new fan speed are formed. The process is then repeated until convergence has been met.

Abstract: A mechanism is provided for minimizing system power in the data processing system with fast convergence. A current aggregate system power value is determined using a current thermal threshold value. For each potential thermal threshold value in a set of potential thermal threshold values, a determination is made as to whether there is a potential thermal threshold value that results in a potential aggregate system power value that is lower than the current aggregate system power value. Responsive to identifying an optimal potential thermal threshold value from the set of potential thermal threshold values that results in minimum aggregate system power value that is lower than the current aggregate system power value, the optimal potential thermal threshold value is set as a new thermal threshold value.

Abstract: A mechanism is provided for minimizing system power in the data processing system with fast convergence. A current aggregate system power value is determined using a current thermal threshold value. For each potential thermal threshold value in a set of potential thermal threshold values, a determination is made as to whether there is a potential thermal threshold value that results in a potential aggregate system power value that is lower than the current aggregate system power value. Responsive to identifying an optimal potential thermal threshold value from the set of potential thermal threshold values that results in minimum aggregate system power value that is lower than the current aggregate system power value, the optimal potential thermal threshold value is set as a new thermal threshold value.

Abstract: A mechanism is provided for dynamically power capping one or more units. A power capping mechanism sets a counter value corresponding to an initial energy budget assigned to a unit for a given interval. Responsive to the unit receiving an operation to perform during the given interval, the power capping mechanism decrements the counter value by a decrement value. Responsive to the given interval expiring, the power capping mechanism sends the counter value to a power control loop in the data processing system, receives a new energy budget from the power control loop, and resets the counter value to a value corresponding to the new energy budget assigned to the unit for a next interval.