Abstract: An IHS configuration system includes a plurality of IHS components including a processor system having a first maximum load current. A power system controller is coupled to the plurality of IHS components and operable to couple to a power supply. The power system controller is operable to retrieve a power output limit of the power system and determine a first system power budget for the plurality of IHS components using the first maximum load current of the processor system. The power system controller then determines whether the first system power budget exceeds the power output limit and, in response to the first system power budget exceeding the power output limit, the power system controller provides a second maximum load current for the processor system to create a second system power budget that does not exceed the power output limit.

Abstract: A voltage regulator phase shedding system includes one or more subsystems to receive a system management interrupt (SMI), gather processor utilization information, determine whether to adjust a performance state, lookup voltage regulator information for new performance state, adjust active voltage regulator phase, and adjust performance state. The voltage regulator phase shedding system can also include one or more subsystems to read a power measurement, calculate throttling requirements, determine whether to adjust a throttling, lookup voltage regulator information for new performance state capacity, adjust active voltage regulator phase, and adjust throttling.

Abstract: A voltage regulator phase shedding system includes one or more subsystems to receive a system management interrupt (SMI), gather processor utilization information, determine whether to adjust a performance state, lookup voltage regulator information for new performance state, adjust active voltage regulator phase, and adjust performance state. The voltage regulator phase shedding system can also include one or more subsystems to read a power measurement, calculate throttling requirements, determine whether to adjust a throttling, lookup voltage regulator information for new performance state capacity, adjust active voltage regulator phase, and adjust throttling.

Abstract: A voltage regulator phase shedding system includes one or more subsystems to receive a system management interrupt (SMI), gather processor utilization information, determine whether to adjust a performance state, lookup voltage regulator information for new performance state, adjust active voltage regulator phase, and adjust performance state. The voltage regulator phase shedding system can also include one or more subsystems to read a power measurement, calculate throttling requirements, determine whether to adjust a throttling, lookup voltage regulator information for new performance state capacity, adjust active voltage regulator phase, and adjust throttling.

Abstract: A switch fabric system comprises a first chassis for receiving a plurality of line cards each having a plurality of ports and at least two switch fabric cards wherein each line card comprises a plurality of link ports for linking the line card with the switch fabric card. Each switch fabric card provides a switching bandwidth. The system comprises a management unit for managing the traffic on the switch fabric cards wherein the management unit removes the traffic from one switch fabric card if the one switch fabric card is to be removed while the other switch fabric card operates and transfers the traffic to the other switch fabric card.

Abstract: A heterogeneous and scalable bridge capable of translating a plurality of network protocols is adapted for coupling to a network switch fabric. The bridge uses at least one egress buffer interface and can perform port aggregation and bandwidth matching for various different port standards. The bridge is adapted for both networking and storage area networking protocols. A control unit is implemented with the bridge is able to identify control and flow information from different protocols and adapt them to the respective interface to which they are to be transmitted. Accounting logic is provided to one or more of the elements of the apparatus to aid in the tracking, storing, and reporting of network traffic.

Abstract: A heterogeneous and scalable bridge capable of translating a plurality of network protocols is adapted for coupling to a network switch fabric. The bridge uses at least one egress buffer interface and can perform port aggregation and bandwidth matching for various different port standards. The bridge is adapted for both networking and storage area networking protocols. A control unit is implemented with the bridge is able to identify control and flow information from different protocols and adapt them to the respective interface to which they are to be transmitted.

Abstract: A system and method for providing flow control for a computer network is disclosed. In one embodiment of the present invention, buffer-to-buffer credit flow control is implemented to limit the amount of data a port may send based on the number and size of the frames sent from that port.

Abstract: A cache-based system is adapted for dynamic cache partitioning. A cache is partitioned into a plurality of cache partitions for a plurality of entities. Each cache partition can be assigned as a private cache for a different entity. If a first cache partition satisfying a first predetermined cache partition condition and a second cache partition satisfying a second predetermined cache partition condition are detected, then the size of the first cache partition is increased by a predetermined segment and the size of the second cache partition is decreased by the predetermined segment. An entity can perform cacheline replacement exclusively in its assigned cache partition, and also be capable of reading any cache partition.

Abstract: A computer system includes a power supply coupled to a control logic, the power supply including a power_good output signal and Power output lines. The power_good signal notifies the control logic when the Power output lines have stabilized. The computer system also includes a plurality of voltage regulator modules (“VRM”) coupled to the control logic, wherein each VRM receives a power good signal from the control logic. A plurality of processors is also present in the computer system, each of the processors coupled to a VRM. Each of the VRMs transmits voltage to a processor to power-on the processor. Each VRM also transmits to its processor and to the control logic a voltage regulator module power good (“VRMP_G”) signal. The control logic includes means to control the sequential power-on of the processors so as to reduce the current sourcing requirements of the power supply and eliminate power supply surges.

Abstract: A cache-based system is adapted for dynamic cache partitioning. A cache is partitioned into a plurality of cache partitions for a plurality of entities. Each cache partition can be assigned as a private cache for a different entity. If a first cache partition satisfying a first predetermined cache partition condition and a second cache partition satisfying a second predetermined cache partition condition are detected, then the size of the first cache partition is increased by a predetermined segment and the size of the second cache partition is decreased by the predetermined segment. An entity can perform cacheline replacement exclusively in its assigned cache partition, and also be capable of reading any cache partition.

Abstract: A cache memory controller allows hot-plug insertion and removal of cache memory modules. After detecting an insertion, the controller waits a predetermined time, then determines the size and speed of the added cache memory modules. If the inserted cache memory module is acceptable, then tag memory is reconfigured to correspond to the inserted memory. The added cache memory is initialized. After successful insertion and initialization, a status bit in the cache controller is set to indicate memory has been added. Prior to removal of a cache memory module, the cache is flushed to main memory and further cache transactions are disabled. After removal of the cache memory module, tag memory is reconfigured to mark a corresponding portion of the tag memory as unused. After successful removal of the cache memory module and reconfiguration of the tag memory, the cache memory controller enables new cache memory transactions.

Abstract: A cache-based system is adapted for dynamic cache partitioning. A cache is partitioned into a plurality of cache partitions for a plurality of entities. Each cache partition can be assigned as a private cache for a different entity. If a first cache partition satisfying a first predetermined cache partition condition and a second cache partition satisfying a second predetermined cache partition condition are detected, then the size of the first cache partition is increased by a predetermined segment and the size of the second cache partition is decreased by the predetermined segment. An entity can perform cacheline replacement exclusively in its assigned cache partition, and also be capable of reading any cache partition.

Abstract: A scalable switch fabric system and apparatus for computer networks. The scalable switch fabric system and apparatus comprises a Switch Fabric Subsystem, Input-Output Subsystems, Application Subsystems and System Control Subsystems. The Switch Fabric Subsystem is a protocol agnostic cell or packet switching infrastructure that provides scalable interconnections between the Input-Output Subsystems and Application Subsystems. The Switch Fabric Subsystem provides primary data paths for network traffic being moved by the switch. The Input-Output Subsystems connect to the external network devices that use the switch to communicate with other external network devices. The Input-Output Subsystems are part of the data path and do low level decoding of ingress frames from the external ports; switching/routing, identifying the destination Input-Output Subsystems for the frame; and queuing the frame for transmission through the Switch Fabric.

Abstract: A computer network switch system is disclosed. A switch system may be configured as a single chassis system that has at least one line card, a set of active switch fabric cards to concurrently carry network traffic; and a first system control card to provide control functionality for the line card. The switch system may be configured as a multiple chassis system that has at least one line card chassis containing several line cards, and a switch fabric chassis (or a second line card chassis) that contains several switch fabric cards to provide a switching fabric with multiple ports. Load-sharing is accomplished primarily at the chip level, although card-level load-sharing is possible.

Abstract: A computer system includes a memory controller that controls and formats transactions with a high speed memory. The memory controller includes a read queue, a write queue, and various other queues in which memory transactions may be stored pending execution. The memory controller periodically executes calibration cycles, such as temperature calibration cycles to the memory to reduce memory errors. The temperature calibration cycles may include an idle state during which no read transactions can be executed. The memory controller includes arbitration logic that reduces latency by issuing read transaction first. Once reads have been issued, the arbitration logic executes any pending temperature cycles. During the idle period of the calibration cycle, the arbitration logic schedules write transactions, and transactions to memory from other queues and devices, including precharge transactions, row activate transactions, refresh cycles, and other calibration cycles.

Abstract: A heterogeneous and scalable bridge capable of translating a plurality of network protocols is adapted for coupling to a network switch fabric. The bridge uses at least one egress buffer interface and can perform port aggregation and bandwidth matching for various different port standards. The bridge is adapted for both networking and storage area networking protocols. A control unit is implemented with the bridge is able to identify control and flow information from different protocols and adapt them to the respective interface to which they are to be transmitted.

Abstract: A system and method for providing XON/XOFF port-level flow control for a computer network that has access to a plurality of network processors in communication with the computer network. At least one network processor has an egress port associated with an egress buffer, and a set of network processors is associated with a bridge.. XON/XOFF port-level flow control is implemented to halt and resume traffic directed to a congested port.

Abstract: A system and method for providing flow control for a computer network is disclosed. In one embodiment of the present invention, buffer-to-buffer credit flow control is implemented to limit the amount of data a port may send based on the number and size of the frames sent from that port.

Abstract: A computer system with high-speed memory devices includes one or more temperature sensors and/or environmental sensors that monitor environmental parameters that may affect the operation of the high-speed memory devices. The sensor values are provided to a control logic in a memory controller, that can intelligently modify the operation of the memory devices in response to changing environmental conditions. Thus, in response to deteriorating environmental conditions, the memory controller may increase the frequency of calibration cycles, or may throttle down the operating speed of the memory devices, or may place some or all of the memory devices in a low power mode until conditions improve. The sensors may be provided on multiple channels, if the memory system is configured with multiple channels, or may be individually associated with memory devices.