Patents by Inventor John Hautala
John Hautala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10629437Abstract: A method may include providing a substrate, comprising a patterning layer. The method may include forming a first pattern of first linear structures in the patterning layer, the first linear structures being elongated along a first direction. The method may include forming a mask over the patterning layer, the mask comprising a second pattern of second linear structures, elongated along a second direction, forming a non-zero angle with respect to the first direction. The method may include selectively removing a portion of the patterning layer while the mask is in place, wherein a first etch pattern is formed in the patterning stack, the first etch pattern comprising a two-dimensional array of cavities. The method may include directionally etching the first etch pattern using an angled ion beam, wherein a second etch pattern is formed, comprising the two-dimensional array of cavities, elongated along the first direction.Type: GrantFiled: August 30, 2018Date of Patent: April 21, 2020Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Sony Varghese, John Hautala, Steven R. Sherman, Rajesh Prasad, Min Gyu Sung
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Publication number: 20200096870Abstract: A method of patterning a substrate may include providing a blanket photoresist layer on the substrate; performing an ion implantation procedure of an implant species into the blanket photoresist layer, the implant species comprising an enhanced absorption efficiency at a wavelength in the extreme ultraviolet (EUV) range; and subsequent to the performing the ion implantation procedure, performing a patterned exposure to expose the blanket photoresist layer to EUV radiation.Type: ApplicationFiled: November 22, 2019Publication date: March 26, 2020Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Tristan Y. Ma, Huixiong Dai, Anthony Renau, John Hautala, Joseph Olson
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Patent number: 10600675Abstract: A method may include providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising an insulator layer and a silicon layer. The silicon layer may be disposed on the insulator layer, where the silicon layer comprises a first silicon thickness variation. The method may include forming an oxide layer on the silicon layer, where the oxide layer has a uniform thickness. The method may include selectively etching the oxide layer on the silicon layer, wherein the oxide layer comprises a first non-uniform oxide thickness. After thermal processing of the SOI substrate in an oxygen ambient, the non-uniform oxide thickness may be configured to generate a second silicon thickness variation in the silicon layer, less than the first silicon thickness variation.Type: GrantFiled: October 9, 2017Date of Patent: March 24, 2020Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Andrew M. Waite, Morgan D. Evans, John Hautala
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Publication number: 20200090909Abstract: A method may include providing a cavity in a surface of a substrate, the cavity comprising a sidewall portion and a lower surface; directing depositing species to the surface of the substrate, wherein the depositing species condense to form a fill material on the sidewall portion and lower surface; and directing angled ions at the cavity at a non-zero angle of incidence with respect to a perpendicular to a plane defined by the substrate, wherein the angled ions strike an exposed part of the sidewall portion and do not strike the lower surface, and wherein the cavity is filled by the fill material in a bottom-up fill process.Type: ApplicationFiled: November 22, 2019Publication date: March 19, 2020Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Simon Ruffell, John Hautala
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Patent number: 10553448Abstract: A method of processing a layer. The method may include providing the layer on a substrate, the substrate defining a substrate plane; directing an ion beam to an exposed surface of the layer in an ion exposure when the substrate is disposed in a first rotational position, the ion beam having a first ion trajectory, the first ion trajectory extending along a first direction, wherein the first ion trajectory forms a non-zero angle of incidence with respect to a perpendicular to the substrate plane; performing a rotation by rotating the substrate with respect to the ion beam about the perpendicular from the first rotational position to a second rotational position; and directing the ion beam to the exposed surface of the layer in an additional ion exposure along the first ion trajectory when the substrate is disposed in the second rotational position.Type: GrantFiled: October 31, 2016Date of Patent: February 4, 2020Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Tristan Y. Ma, Morgan Evans, Kevin Anglin, Robert J. Masci, John Hautala
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Patent number: 10546730Abstract: A method may include providing a cavity in a surface of a substrate, the cavity comprising a sidewall portion and a lower surface; directing depositing species to the surface of the substrate, wherein the depositing species condense to form a fill material on the sidewall portion and lower surface; and directing angled ions at the cavity at a non-zero angle of incidence with respect to a perpendicular to a plane defined by the substrate, wherein the angled ions strike an exposed part of the sidewall portion and do not strike the lower surface, and wherein the cavity is filled by the fill material in a bottom-up fill process.Type: GrantFiled: May 16, 2016Date of Patent: January 28, 2020Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INCInventors: Simon Ruffell, John Hautala
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Patent number: 10545408Abstract: A method of patterning a substrate may include providing a blanket photoresist layer on the substrate; performing an ion implantation procedure of an implant species into the blanket photoresist layer, the implant species comprising an enhanced absorption efficiency at a wavelength in the extreme ultraviolet (EUV) range; and subsequent to the performing the ion implantation procedure, performing a patterned exposure to expose the blanket photoresist layer to EUV radiation.Type: GrantFiled: October 18, 2017Date of Patent: January 28, 2020Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Tristan Y. Ma, Huixiong Dai, Anthony Renau, John Hautala, Joseph Olson
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Publication number: 20200027733Abstract: A method for patterning a three-dimensional structure is provided. The method may include providing a substrate, the substrate including the three-dimensional structure, and directing a depositing species from a deposition source to the three-dimensional structure, wherein a layer forms on the three-dimensional structure. The method may further include directing angled ions to the three-dimensional structure from an ion source, wherein the angled ions impinge on a first region of the layer and do not impinge on a second region of the layer. As such, the first region may form a densified layer portion having a first density, and the second region may form an undensified layer portion having a second density, less than the first density.Type: ApplicationFiled: July 20, 2018Publication date: January 23, 2020Applicant: Varian Semiconductor Equipment Associates, Inc.Inventor: JOHN HAUTALA
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Publication number: 20200027832Abstract: A method of forming a device may include forming a component in a first level of a device structure; forming a contact cavity overlapping the component, the contact cavity forming a non-zero angle of inclination with respect to a perpendicular to a substrate plane. The method may further include filling the contact cavity with a conductor, wherein an angled conductor is formed, wherein the angled conductor extends to a second level of the device structure.Type: ApplicationFiled: July 17, 2018Publication date: January 23, 2020Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Sony Varghese, Anthony Renau, Morgan Evans, John Hautala, Joe Olson, Min Gyu Sung
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Publication number: 20190348287Abstract: A method may include providing a substrate, comprising a patterning layer. The method may include forming a first pattern of first linear structures in the patterning layer, the first linear structures being elongated along a first direction. The method may include forming a mask over the patterning layer, the mask comprising a second pattern of second linear structures, elongated along a second direction, forming a non-zero angle with respect to the first direction. The method may include selectively removing a portion of the patterning layer while the mask is in place, wherein a first etch pattern is formed in the patterning stack, the first etch pattern comprising a two-dimensional array of cavities. The method may include directionally etching the first etch pattern using an angled ion beam, wherein a second etch pattern is formed, comprising the two-dimensional array of cavities, elongated along the first direction.Type: ApplicationFiled: August 30, 2018Publication date: November 14, 2019Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Sony Varghese, John Hautala, Steven R. Sherman, Rajesh Prasad, Min Gyu Sung
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Patent number: 10403738Abstract: Methods for forming three-dimensional transistor devices. In one embodiment a method of forming a three-dimensional transistor device may include providing a substrate comprising a semiconductor device structure, the semiconductor device structure comprising a nanowire stack, a gate stack disposed above the nanowire stack, and an inner spacer layer, disposed over the gate stack and the nanowire stack. The method may further include directing ions at the semiconductor device structure, wherein an altered layer is formed in a first part of the inner spacer layer, and an unaltered portion of the inner spacer layer remains, subjacent to the altered layer.Type: GrantFiled: July 20, 2018Date of Patent: September 3, 2019Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Min Gyu Sung, Rajesh Prasad, John Hautala, Sony Varghese
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Publication number: 20190258008Abstract: An optical grating component may include a substrate, and an optical grating, the optical grating being disposed on the substrate. The optical grating may include a plurality of angled structures, disposed at a non-zero angle of inclination with respect to a perpendicular to a plane of the substrate, wherein the plurality of angled structures are arranged to define a variable depth along a first direction, the first direction being parallel to the plane of the substrate.Type: ApplicationFiled: February 21, 2018Publication date: August 22, 2019Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: John Hautala, Morgan Evans, Rutger Meyer Timmerman Thijssen, Joseph C. Olson
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Patent number: 10381232Abstract: A method may include providing a surface feature on a substrate, the surface feature comprising a feature shape a feature location, and a dimension along a first direction within a substrate plane; depositing a layer comprising a layer material on the surface feature; and directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane, wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the surface feature and do not impact a second portion of the surface feature, and wherein an altered surface feature is generated, the altered surface feature differing from the surface feature in at least one of: the dimension along the first direction, the feature shape, or the feature location.Type: GrantFiled: May 11, 2018Date of Patent: August 13, 2019Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Simon Ruffell, Huixiong Dai, Jun Lang, John Hautala
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Publication number: 20190181144Abstract: A memory device may include an active device region, disposed at least partially in a first level. The memory device may include a storage capacitor, disposed at least partially in a second level, above the first level, wherein the first level and the second level are parallel to a substrate plane. The memory device may also include a contact via, the contact via extending between the storage capacitor and the active device region, and defining a non-zero angle of inclination with respect to a perpendicular to the substrate plane.Type: ApplicationFiled: December 12, 2017Publication date: June 13, 2019Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Sony Varghese, Anthony Renau, Morgan Evans, John Hautala, Joe Olson
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Patent number: 10310379Abstract: A method for patterning a substrate, comprising: providing a photoresist patterning feature on the substrate, the substrate defining a substrate plane, the photoresist patterning feature having a softening temperature below 200° C. The method may include directing a first ion species into the photoresist patterning feature during a first exposure; and depositing a sidewall layer on the patterning feature after the directing at a deposition temperature, the deposition temperature being 200° C. or greater.Type: GrantFiled: March 14, 2017Date of Patent: June 4, 2019Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Tristan Y. Ma, Maureen K. Petterson, John Hautala, Steven R. Sherman
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Patent number: 10229832Abstract: A method of patterning a substrate. The method may include: providing a first surface feature and a second surface feature in a staggered configuration within a layer, the layer being disposed on the substrate, and directing first ions in a first exposure to a first side of the first surface feature and a first side of the second surface feature, in a presence of a reactive ambient containing a reactive species, wherein the first exposure etches the first side of the first surface feature and the first side of the second surface feature, wherein after the directing, the first surface feature and the second surface feature merge to form a third surface feature.Type: GrantFiled: December 20, 2016Date of Patent: March 12, 2019Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Steven R. Sherman, John Hautala, Simon Ruffell
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Publication number: 20190056914Abstract: A method of patterning a substrate may include providing a blanket photoresist layer on the substrate; performing an ion implantation procedure of an implant species into the blanket photoresist layer, the implant species comprising an enhanced absorption efficiency at a wavelength in the extreme ultraviolet (EUV) range; and subsequent to the performing the ion implantation procedure, performing a patterned exposure to expose the blanket photoresist layer to EUV radiation.Type: ApplicationFiled: October 18, 2017Publication date: February 21, 2019Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Tristan Y. Ma, Huixiong Dai, Anthony Renau, John Hautala, Joseph Olson
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Patent number: 10204909Abstract: Provided herein are approaches for forming a gate oxide layer for a DRAM device, the method including providing a finned substrate having a recess formed therein, and performing an ion implant into a sidewall surface of the recess to form a gate oxide layer having a non-uniform thickness, wherein a thickness of the gate oxide layer at a top section of the sidewall surface is greater than a thickness of the gate oxide layer at a bottom section of the sidewall surface. In some approaches, the ion implant is provided as a series of ion implants at multiple different implant angles, varied along with an ion implantation energy and/or an ion dose to increase the thickness of the gate oxide of the top section of the sidewall surface. In some approaches, the finned substrate is also exposed to a plasma, either during or after, the ion implantation.Type: GrantFiled: December 22, 2015Date of Patent: February 12, 2019Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Simon Ruffell, Arvind Kumar, Tristan Ma, Kyu-Ha Shim, John Hautala, Steven Sherman
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Publication number: 20190027396Abstract: A method may include providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising an insulator layer and a silicon layer. The silicon layer may be disposed on the insulator layer, where the silicon layer comprises a first silicon thickness variation. The method may include forming an oxide layer on the silicon layer, where the oxide layer has a uniform thickness. The method may include selectively etching the oxide layer on the silicon layer, wherein the oxide layer comprises a first non-uniform oxide thickness. After thermal processing of the SOI substrate in an oxygen ambient, the non-uniform oxide thickness may be configured to generate a second silicon thickness variation in the silicon layer, less than the first silicon thickness variation.Type: ApplicationFiled: October 9, 2017Publication date: January 24, 2019Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Andrew M. Waite, Morgan D. Evans, John Hautala
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Publication number: 20180330944Abstract: A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.Type: ApplicationFiled: May 14, 2018Publication date: November 15, 2018Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Simon Ruffell, John Hautala, Adam Brand, Huixiong Dai