Patents by Inventor John Williams Palmour
John Williams Palmour has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11171229Abstract: The present disclosure relates to a power module that has a housing with an interior chamber and a plurality of switch modules interconnected to facilitate switching power to a load. Each of the plurality of switch modules comprises at least one transistor and at least one diode mounted within the interior chamber and both the at least one transistor and the at least one diode are majority carrier devices, are formed of a wide bandgap material system, or both. The switching modules may be arranged in virtually any fashion depending on the application. For example, the switching modules may be arranged in a six-pack, full H-bridge, half H-bridge, single switch or the like.Type: GrantFiled: April 10, 2017Date of Patent: November 9, 2021Assignee: Cree, Inc.Inventors: Mrinal K. Das, Robert J. Callanan, Henry Lin, John Williams Palmour
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Patent number: 11024731Abstract: A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm2.Type: GrantFiled: October 26, 2018Date of Patent: June 1, 2021Assignee: Cree, Inc.Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Kumar Agarwal, John Williams Palmour, Scott Allen
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Patent number: 10950719Abstract: A vertical field-effect transistor (FET) device includes a monolithically integrated bypass diode connected between a source contact and a drain contact of the vertical FET device. According to one embodiment, the vertical FET device includes a pair of junction implants separated by a junction field-effect transistor (JFET) region. At least one of the junction implants of the vertical FET device includes a deep well region that is shared with the integrated bypass diode, such that the shared deep well region functions as both a source junction in the vertical FET device and a junction barrier region in the integrated bypass diode. The vertical FET device and the integrated bypass diode may include a substrate, a drift layer over the substrate, and a spreading layer over the drift layer, such that the junction implants of the vertical FET device are formed in the spreading layer.Type: GrantFiled: April 17, 2014Date of Patent: March 16, 2021Assignee: Cree, Inc.Inventors: Vipindas Pala, Lin Cheng, Anant Kumar Agarwal, John Williams Palmour, Edward Robert Van Brunt
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Patent number: 10910481Abstract: A semiconductor device includes a semiconductor body and an insulated gate contact on a surface of the semiconductor body over an active channel in the semiconductor device. The insulated gate contact includes a channel mobility enhancement layer on the surface of the semiconductor body, a diffusion barrier layer over the channel mobility enhancement layer, and a dielectric layer over the diffusion barrier layer. By using the channel mobility enhancement layer in the insulated gate contact, the mobility of the semiconductor device is improved. Further, by using the diffusion barrier layer, the integrity of the gate oxide is retained, resulting in a robust semiconductor device with a low on-state resistance.Type: GrantFiled: November 5, 2014Date of Patent: February 2, 2021Assignee: Cree, Inc.Inventors: Daniel Jenner Lichtenwalner, Lin Cheng, John Williams Palmour
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Patent number: 10868169Abstract: A vertical field-effect transistor (FET) device includes a monolithically integrated bypass diode connected between a source contact and a drain contact of the vertical FET device. According to one embodiment, the vertical FET device includes a pair of junction implants separated by a junction field-effect transistor (JFET) region. At least one of the junction implants of the vertical FET device includes a deep well region that is shared with the integrated bypass diode, such that the shared deep well region functions as both a source junction in the vertical FET device and a junction barrier region in the integrated bypass diode. The vertical FET device and the integrated bypass diode may include a substrate, a drift layer over the substrate, and a spreading layer over the drift layer, such that the junction implants of the vertical FET device are formed in the spreading layer.Type: GrantFiled: September 20, 2013Date of Patent: December 15, 2020Assignee: Cree, Inc.Inventors: Vipindas Pala, Lin Cheng, Anant Kumar Agarwal, John Williams Palmour, Edward Robert Van Brunt
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Publication number: 20190067468Abstract: A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm2.Type: ApplicationFiled: October 26, 2018Publication date: February 28, 2019Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Kumar Agarwal, John Williams Palmour, Scott Allen
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Patent number: 10153364Abstract: A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm2.Type: GrantFiled: April 10, 2017Date of Patent: December 11, 2018Assignee: Cree, Inc.Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Kumar Agarwal, John Williams Palmour, Scott Allen
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Patent number: 10141302Abstract: A power module includes a housing with an interior chamber and multiple switch modules mounted within the interior chamber of the housing. The switch modules are interconnected and configured to facilitate switching power to a load. Each one of the switch modules includes at least one transistor and at least one diode. The at least one transistor and the at least one diode may be formed from a wide band-gap material system, such as silicon carbide (SiC), thereby allowing the power module to operate at high frequencies with lower switching losses when compared to conventional power modules.Type: GrantFiled: March 22, 2016Date of Patent: November 27, 2018Assignee: Cree, Inc.Inventors: Mrinal K. Das, Henry Lin, Marcelo Schupbach, John Williams Palmour
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Patent number: 9991399Abstract: A Schottky diode is disclosed that includes a silicon carbide substrate, a silicon carbide drift layer, a Schottky contact, and a passivation structure. The silicon carbide drift layer provides an active region and an edge termination region about the active region. The Schottky contact has sides and a top extending between the two sides and includes a Schottky layer over the active region and an anode contact over the Schottky layer. The passivation structure covers the edge termination region, the sides of the Schottky contact, and at least a portion of the top of the Schottky contact. The passivation structure includes a first silicon nitride layer, a silicon dioxide layer over the first silicon nitride layer, and a second silicon nitride layer over the silicon dioxide layer.Type: GrantFiled: September 26, 2014Date of Patent: June 5, 2018Assignee: Cree, Inc.Inventors: Van Mieczkowski, Jonathan Young, Qingchun Zhang, John Williams Palmour
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Patent number: 9865750Abstract: The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.Type: GrantFiled: July 28, 2015Date of Patent: January 9, 2018Assignee: Cree, Inc.Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Kumar Agarwal, John Williams Palmour, Scott Allen
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Publication number: 20170263713Abstract: A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm2.Type: ApplicationFiled: April 10, 2017Publication date: September 14, 2017Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Kumar Agarwal, John Williams Palmour, Scott Allen
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Patent number: 9741842Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.Type: GrantFiled: March 31, 2016Date of Patent: August 22, 2017Assignee: Cree, Inc.Inventors: Vipindas Pala, Anant Kumar Agarwal, Lin Cheng, Daniel Jenner Lichtenwalner, John Williams Palmour
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Publication number: 20170213811Abstract: The present disclosure relates to a power module that has a housing with an interior chamber and a plurality of switch modules interconnected to facilitate switching power to a load. Each of the plurality of switch modules comprises at least one transistor and at least one diode mounted within the interior chamber and both the at least one transistor and the at least one diode are majority carrier devices, are formed of a wide bandgap material system, or both. The switching modules may be arranged in virtually any fashion depending on the application. For example, the switching modules may be arranged in a six-pack, full H-bridge, half H-bridge, single switch or the like.Type: ApplicationFiled: April 10, 2017Publication date: July 27, 2017Inventors: Mrinal K. Das, Robert J. Callanan, Henry Lin, John Williams Palmour
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Patent number: 9673283Abstract: A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm2.Type: GrantFiled: August 17, 2012Date of Patent: June 6, 2017Assignee: Cree, Inc.Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Kumar Agarwal, John Williams Palmour, Scott Allen
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Patent number: 9640617Abstract: The present disclosure relates to a power module that has a housing with an interior chamber and a plurality of switch modules interconnected to facilitate switching power to a load. Each of the plurality of switch modules comprises at least one transistor and at least one diode mounted within the interior chamber and both the at least one transistor and the at least one diode are majority carrier devices, are formed of a wide bandgap material system, or both. The switching modules may be arranged in virtually any fashion depending on the application. For example, the switching modules may be arranged in a six-pack, full H-bridge, half H-bridge, single switch or the like.Type: GrantFiled: May 14, 2013Date of Patent: May 2, 2017Assignee: Cree, Inc.Inventors: Mrinal K. Das, Robert J. Callanan, Henry Lin, John Williams Palmour
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Patent number: 9570570Abstract: The present disclosure relates to a silicon carbide (SiC) field effect device that has a gate assembly formed in a trench. The gate assembly includes a gate dielectric that is an dielectric layer, which is deposited along the inside surface of the trench and a gate dielectric formed over the gate dielectric. The trench extends into the body of the device from a top surface and has a bottom and side walls that extend from the top surface of the body to the bottom of the trench. The thickness of the dielectric layer on the bottom of the trench is approximately equal to or greater than the thickness of the dielectric layer on the side walls of the trench.Type: GrantFiled: July 17, 2013Date of Patent: February 14, 2017Assignee: Cree, Inc.Inventors: Daniel Jenner Lichtenwalner, Lin Cheng, Anant Kumar Agarwal, John Williams Palmour
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Publication number: 20160211360Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.Type: ApplicationFiled: March 31, 2016Publication date: July 21, 2016Inventors: Vipindas Pala, Anant Kumar Agarwal, Lin Cheng, Daniel Jenner Lichtenwalner, John Williams Palmour
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Patent number: RE48380Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.Type: GrantFiled: May 3, 2018Date of Patent: January 5, 2021Assignee: Cree, Inc.Inventors: Vipindas Pala, Anant Kumar Agarwal, Lin Cheng, Daniel Jenner Lichtenwalner, John Williams Palmour
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Patent number: RE49167Abstract: A Schottky diode is disclosed that includes a silicon carbide substrate, a silicon carbide drift layer, a Schottky contact, and a passivation structure. The silicon carbide drift layer provides an active region and an edge termination region about the active region. The Schottky contact has sides and a top extending between the two sides and includes a Schottky layer over the active region and an anode contact over the Schottky layer. The passivation structure covers the edge termination region, the sides of the Schottky contact, and at least a portion of the top of the Schottky contact. The passivation structure includes a first silicon nitride layer, a silicon dioxide layer over the first silicon nitride layer, and a second silicon nitride layer over the silicon dioxide layer.Type: GrantFiled: November 12, 2019Date of Patent: August 9, 2022Assignee: WOLFSPEED, INC.Inventors: Van Mieczkowski, Jonathan Young, Qingchun Zhang, John Williams Palmour
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Patent number: RE49913Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.Type: GrantFiled: October 26, 2020Date of Patent: April 9, 2024Assignee: Wolfspeed, Inc.Inventors: Vipindas Pala, Anant Kumar Agarwal, Lin Cheng, Daniel Jenner Lichtenwalner, John Williams Palmour