Patents by Inventor John Williams Palmour
John Williams Palmour has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9396946Abstract: Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.Type: GrantFiled: September 9, 2011Date of Patent: July 19, 2016Assignee: Cree, Inc.Inventors: Sarit Dhar, Lin Cheng, Sei-Hyung Ryu, Anant Agarwal, John Williams Palmour, Erik Maki, Jason Gurganus, Daniel Jenner Lichtenwalner
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Publication number: 20160204101Abstract: A power module includes a housing with an interior chamber and multiple switch modules mounted within the interior chamber of the housing. The switch modules are interconnected and configured to facilitate switching power to a load. Each one of the switch modules includes at least one transistor and at least one diode. The at least one transistor and the at least one diode may be formed from a wide band-gap material system, such as silicon carbide (SiC), thereby allowing the power module to operate at high frequencies with lower switching losses when compared to conventional power modules.Type: ApplicationFiled: March 22, 2016Publication date: July 14, 2016Inventors: Mrinal K. Das, Henry Lin, Marcelo Schupbach, John Williams Palmour
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Patent number: 9373617Abstract: A power module includes a housing with an interior chamber and multiple switch modules mounted within the interior chamber of the housing. The switch modules are interconnected and configured to facilitate switching power to a load. Each one of the switch modules includes at least one transistor and at least one diode. The at least one transistor and the at least one diode may be formed from a wide band-gap material system, such as silicon carbide (SiC), thereby allowing the power module to operate at high frequencies with lower switching losses when compared to conventional power modules.Type: GrantFiled: May 15, 2014Date of Patent: June 21, 2016Assignee: Cree, Inc.Inventors: Mrinal K. Das, Henry Lin, Marcelo Schupbach, John Williams Palmour
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Patent number: 9349797Abstract: The present disclosure relates to a Silicon Carbide (SiC) semiconductor device having both a high blocking voltage and low on-resistance. In one embodiment, the semiconductor device has a blocking voltage of at least 10 kilovolts (kV) and an on-resistance of less than 10 milli-ohms centimeter squared (m?·cm2) and even more preferably less than 5 m?·cm2. In another embodiment, the semiconductor device has a blocking voltage of at least 15 kV and an on-resistance of less than 15 m?·cm2 and even more preferably less than 7 m?·cm2. In yet another embodiment, the semiconductor device has a blocking voltage of at least 20 kV and an on-resistance of less than 20 m?·cm2 and even more preferably less than 10 m?·cm2. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), or a PIN diode.Type: GrantFiled: February 6, 2012Date of Patent: May 24, 2016Assignee: Cree, Inc.Inventors: Lin Cheng, Anant K. Agarwal, Michael John O'Loughlin, Albert Augustus Burk, Jr., John Williams Palmour
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Publication number: 20160126333Abstract: A semiconductor device includes a semiconductor body and an insulated gate contact on a surface of the semiconductor body over an active channel in the semiconductor device. The insulated gate contact includes a channel mobility enhancement layer on the surface of the semiconductor body, a diffusion barrier layer over the channel mobility enhancement layer, and a dielectric layer over the diffusion barrier layer. By using the channel mobility enhancement layer in the insulated gate contact, the mobility of the semiconductor device is improved. Further, by using the diffusion barrier layer, the integrity of the gate oxide is retained, resulting in a robust semiconductor device with a low on-state resistance.Type: ApplicationFiled: November 5, 2014Publication date: May 5, 2016Inventors: Daniel Jenner Lichtenwalner, Lin Cheng, John Williams Palmour
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Patent number: 9331197Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.Type: GrantFiled: August 8, 2013Date of Patent: May 3, 2016Assignee: Cree, Inc.Inventors: Vipindas Pala, Anant Kumar Agarwal, Lin Cheng, Daniel Jenner Lichtenwalner, John Williams Palmour
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Patent number: 9318597Abstract: A semiconductor device includes a vertical field-effect-transistor (FET) and a bypass diode. The vertical FET device includes a substrate, a drift layer formed over the substrate, a gate contact and a plurality of source contacts located on a first surface of the drift layer opposite the substrate, a drain contact located on a surface of the substrate opposite the drift layer, and a plurality of junction implants, each of the plurality of junction implants laterally separated from one another on the surface of the drift layer opposite the substrate and extending downward toward the substrate. Each of the one or more bypass diodes are formed by placing a Schottky metal contact on the first surface of the drift layer, such that each Schottky metal contact runs between two of the plurality of junction implants.Type: GrantFiled: September 20, 2013Date of Patent: April 19, 2016Assignee: Cree, Inc.Inventors: Vipindas Pala, Edward Robert Van Brunt, Lin Cheng, John Williams Palmour
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Publication number: 20160093748Abstract: A Schottky diode is disclosed that includes a silicon carbide substrate, a silicon carbide drift layer, a Schottky contact, and a passivation structure. The silicon carbide drift layer provides an active region and an edge termination region about the active region. The Schottky contact has sides and a top extending between the two sides and includes a Schottky layer over the active region and an anode contact over the Schottky layer. The passivation structure covers the edge termination region, the sides of the Schottky contact, and at least a portion of the top of the Schottky contact. The passivation structure includes a first silicon nitride layer, a silicon dioxide layer over the first silicon nitride layer, and a second silicon nitride layer over the silicon dioxide layer.Type: ApplicationFiled: September 26, 2014Publication date: March 31, 2016Inventors: Van Mieczkowski, Jonathan Young, Qingchun Zhang, John Williams Palmour
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Patent number: 9269580Abstract: Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.Type: GrantFiled: September 9, 2011Date of Patent: February 23, 2016Assignee: Cree, Inc.Inventors: Sarit Dhar, Lin Cheng, Sei-Hyung Ryu, Anant Agarwal, John Williams Palmour, Jason Gurganus
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Patent number: 9236433Abstract: A Silicon Carbide (SiC) semiconductor device having back-side contacts to a P-type region and methods of fabrication thereof are disclosed. In one embodiment, an SiC semiconductor device includes an N-type substrate and an epitaxial structure on a front-side of the N-type substrate. The epitaxial substrate includes a P-type layer adjacent to the N-type substrate and one or more additional SiC layers on the P-type layer opposite the N-type substrate. The semiconductor device also includes one or more openings through the N-type substrate that extend from a back-side of the N-type substrate to the P-type layer and a back-side contact on the back-side of the N-type substrate and within the one or more openings such that the back-side contact is in physical and electrical contact with the P-type layer. The semiconductor device further includes front-side contacts on the epitaxial structure opposite the N-type substrate.Type: GrantFiled: October 10, 2013Date of Patent: January 12, 2016Assignee: Cree, Inc.Inventors: Vipindas Pala, Edward Robert Van Brunt, Daniel Jenner Lichtenwalner, Lin Cheng, Anant Kumar Agarwal, John Williams Palmour
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Patent number: 9231122Abstract: The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.Type: GrantFiled: January 31, 2014Date of Patent: January 5, 2016Assignee: Cree, Inc.Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Kumar Agarwal, John Williams Palmour, Scott Allen
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Publication number: 20150333191Abstract: The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.Type: ApplicationFiled: July 28, 2015Publication date: November 19, 2015Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Kumar Agarwal, John Williams Palmour, Scott Allen
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Patent number: 9111919Abstract: A vertically oriented field effect device has a body and an enhance gate structure. The body includes a JFET (junction field effect transistor) region disposed between junction implants that extend into the body from a top surface of the body. The gate structure includes a supplemental gate dielectric, a primary gate dielectric, and a gate contact. The supplemental gate dielectric is formed over the top surface of the body above the JFET region, such that the supplemental dielectric is separated from the junction implants by a gap. The primary gate dielectric is formed over the supplemental gate dielectric, above the gap over the top surface of the body, and over at least a portion of the junction implants. The gate contact is formed over the primary gate dielectric.Type: GrantFiled: October 3, 2013Date of Patent: August 18, 2015Assignee: Cree, Inc.Inventors: Daniel Jenner Lichtenwalner, Anant Kumar Agarwal, Lin Cheng, Vipindas Pala, John Williams Palmour
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Publication number: 20150102361Abstract: A Silicon Carbide (SiC) semiconductor device having back-side contacts to a P-type region and methods of fabrication thereof are disclosed. In one embodiment, an SiC semiconductor device includes an N-type substrate and an epitaxial structure on a front-side of the N-type substrate. The epitaxial substrate includes a P-type layer adjacent to the N-type substrate and one or more additional SiC layers on the P-type layer opposite the N-type substrate. The semiconductor device also includes one or more openings through the N-type substrate that extend from a back-side of the N-type substrate to the P-type layer and a back-side contact on the back-side of the N-type substrate and within the one or more openings such that the back-side contact is in physical and electrical contact with the P-type layer. The semiconductor device further includes front-side contacts on the epitaxial structure opposite the N-type substrate.Type: ApplicationFiled: October 10, 2013Publication date: April 16, 2015Applicant: Cree, Inc.Inventors: Vipindas Pala, Edward Robert Van Brunt, Daniel Jenner Lichtenwalner, Lin Cheng, Anant Kumar Agarwal, John Williams Palmour
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Publication number: 20150097226Abstract: A vertically oriented field effect device has a body and an enhance gate structure. The body includes a JFET (junction field effect transistor) region disposed between junction implants that extend into the body from a top surface of the body. The gate structure includes a supplemental gate dielectric, a primary gate dielectric, and a gate contact. The supplemental gate dielectric is formed over the top surface of the body above the JFET region, such that the supplemental dielectric is separated from the junction implants by a gap. The primary gate dielectric is formed over the supplemental gate dielectric, above the gap over the top surface of the body, and over at least a portion of the junction implants. The gate contact is formed over the primary gate dielectric.Type: ApplicationFiled: October 3, 2013Publication date: April 9, 2015Applicant: Cree, Inc.Inventors: Daniel Jenner Lichtenwalner, Anant Kumar Agarwal, Lin Cheng, Vipindas Pala, John Williams Palmour
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Publication number: 20150084125Abstract: A vertical field-effect transistor (FET) device includes a monolithically integrated bypass diode connected between a source contact and a drain contact of the vertical FET device. According to one embodiment, the vertical FET device includes a pair of junction implants separated by a junction field-effect transistor (JFET) region. At least one of the junction implants of the vertical FET device includes a deep well region that is shared with the integrated bypass diode, such that the shared deep well region functions as both a source junction in the vertical FET device and a junction barrier region in the integrated bypass diode. The vertical FET device and the integrated bypass diode may include a substrate, a drift layer over the substrate, and a spreading layer over the drift layer, such that the junction implants of the vertical FET device are formed in the spreading layer.Type: ApplicationFiled: September 20, 2013Publication date: March 26, 2015Applicant: CREE, INC.Inventors: Vipindas Pala, Lin Cheng, Anant Kumar Agarwal, John Williams Palmour, Edward Robert Van Brunt
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Publication number: 20150084062Abstract: A vertical field-effect transistor (FET) device includes a monolithically integrated bypass diode connected between a source contact and a drain contact of the vertical FET device. According to one embodiment, the vertical FET device includes a pair of junction implants separated by a junction field-effect transistor (JFET) region. At least one of the junction implants of the vertical FET device includes a deep well region that is shared with the integrated bypass diode, such that the shared deep well region functions as both a source junction in the vertical FET device and a junction barrier region in the integrated bypass diode. The vertical FET device and the integrated bypass diode may include a substrate, a drift layer over the substrate, and a spreading layer over the drift layer, such that the junction implants of the vertical FET device are formed in the spreading layer.Type: ApplicationFiled: April 17, 2014Publication date: March 26, 2015Applicant: Cree, Inc.Inventors: Vipindas Pala, Lin Cheng, Anant Kumar Agarwal, John Williams Palmour, Edward Robert Van Brunt
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Publication number: 20150084119Abstract: A semiconductor device includes a vertical field-effect-transistor (FET) and a bypass diode. The vertical FET device includes a substrate, a drift layer formed over the substrate, a gate contact and a plurality of source contacts located on a first surface of the drift layer opposite the substrate, a drain contact located on a surface of the substrate opposite the drift layer, and a plurality of junction implants, each of the plurality of junction implants laterally separated from one another on the surface of the drift layer opposite the substrate and extending downward toward the substrate. Each of the one or more bypass diodes are formed by placing a Schottky metal contact on the first surface of the drift layer, such that each Schottky metal contact runs between two of the plurality of junction implants.Type: ApplicationFiled: September 20, 2013Publication date: March 26, 2015Applicant: Cree, Inc.Inventors: Vipindas Pala, Edward Robert Van Brunt, Lin Cheng, John Williams Palmour
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Publication number: 20150041886Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.Type: ApplicationFiled: August 8, 2013Publication date: February 12, 2015Applicant: Cree, Inc.Inventors: Vipindas Pala, Anant Kumar Agarwal, Lin Cheng, Daniel Jenner Lichtenwalner, John Williams Palmour
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Publication number: 20150021623Abstract: The present disclosure relates to a silicon carbide (SiC) field effect device that has a gate assembly formed in a trench. The gate assembly includes a gate dielectric that is an dielectric layer, which is deposited along the inside surface of the trench and a gate dielectric formed over the gate dielectric. The trench extends into the body of the device from a top surface and has a bottom and side walls that extend from the top surface of the body to the bottom of the trench. The thickness of the dielectric layer on the bottom of the trench is approximately equal to or greater than the thickness of the dielectric layer on the side walls of the trench.Type: ApplicationFiled: July 17, 2013Publication date: January 22, 2015Inventors: Daniel Jenner Lichtenwalner, Lin Cheng, Anant Kumar Agarwal, John Williams Palmour