Patents by Inventor John Williams Palmour
John Williams Palmour has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20140246681Abstract: A power module includes a housing with an interior chamber and multiple switch modules mounted within the interior chamber of the housing. The switch modules are interconnected and configured to facilitate switching power to a load. Each one of the switch modules includes at least one transistor and at least one diode. The at least one transistor and the at least one diode may be formed from a wide band-gap material system, such as silicon carbide (SiC), thereby allowing the power module to operate at high frequencies with lower switching losses when compared to conventional power modules.Type: ApplicationFiled: May 15, 2014Publication date: September 4, 2014Applicant: Cree, Inc.Inventors: Mrinal K. Das, Henry Lin, Marcelo Schupbach, John Williams Palmour
-
Publication number: 20140145213Abstract: The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.Type: ApplicationFiled: January 31, 2014Publication date: May 29, 2014Applicant: Cree, Inc.Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Kumar Agarwal, John Williams Palmour, Scott Allen
-
Patent number: 8680587Abstract: The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.Type: GrantFiled: September 11, 2011Date of Patent: March 25, 2014Assignee: Cree, Inc.Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Agarwal, John Williams Palmour, Scott Allen
-
Patent number: 8664665Abstract: The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the substrate. A junction barrier array is provided in the drift layer just below the Schottky layer. The elements of the junction barrier array are generally doped regions in the drift layer. To increase the depth of these doped regions, individual recesses may be formed in the surface of the drift layer where the elements of the junction barrier array are to be formed. Once the recesses are formed in the drift layer, areas about and at the bottom of the recesses are doped to form the respective elements of the junction barrier array.Type: GrantFiled: September 11, 2011Date of Patent: March 4, 2014Assignee: Cree, Inc.Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Agarwal, John Williams Palmour, Scott Allen
-
Patent number: 8618582Abstract: Elements of an edge termination structure, such as multiple concentric guard rings, are effectively doped regions in a drift layer. To increase the depth of these doped regions, individual recesses may be formed in a surface of the drift layer where the elements of the edge termination structure are to be formed. Once the recesses are formed in the drift layer, these areas about and at the bottom of the recesses are doped to form the respective edge termination elements.Type: GrantFiled: September 11, 2011Date of Patent: December 31, 2013Assignee: Cree, Inc.Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Agarwal, John Williams Palmour, Scott Allen
-
Publication number: 20130207123Abstract: A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm2.Type: ApplicationFiled: August 17, 2012Publication date: August 15, 2013Applicant: CREE, INC.Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Kumar Agarwal, John Williams Palmour, Scott Allen
-
Publication number: 20130062723Abstract: The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.Type: ApplicationFiled: September 11, 2011Publication date: March 14, 2013Applicant: CREE, INC.Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Agarwal, John Williams Palmour, Scott Allen
-
Publication number: 20130062620Abstract: The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the substrate. A junction barrier array is provided in the drift layer just below the Schottky layer. The elements of the junction barrier array are generally doped regions in the drift layer. To increase the depth of these doped regions, individual recesses may be formed in the surface of the drift layer where the elements of the junction barrier array are to be formed. Once the recesses are formed in the drift layer, areas about and at the bottom of the recesses are doped to form the respective elements of the junction barrier array.Type: ApplicationFiled: September 11, 2011Publication date: March 14, 2013Applicant: CREE, INC.Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Agarwal, John Williams Palmour, Scott Allen
-
Publication number: 20130062619Abstract: Elements of an edge termination structure, such as multiple concentric guard rings, are effectively doped regions in a drift layer. To increase the depth of these doped regions, individual recesses may be formed in a surface of the drift layer where the elements of the edge termination structure are to be formed. Once the recesses are formed in the drift layer, these areas about and at the bottom of the recesses are doped to form the respective edge termination elements.Type: ApplicationFiled: September 11, 2011Publication date: March 14, 2013Applicant: CREE, INC.Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Agarwal, John Williams Palmour, Scott Allen
-
Publication number: 20130026493Abstract: The present disclosure relates to a Silicon Carbide (SiC) semiconductor device having both a high blocking voltage and low on-resistance. In one embodiment, the semiconductor device has a blocking voltage of at least 10 kilovolts (kV) and an on-resistance of less than 10 milli-ohms centimeter squared (m?·cm2) and even more preferably less than 5 m?·cm2. In another embodiment, the semiconductor device has a blocking voltage of at least 15 kV and an on-resistance of less than 15 m?·cm2 and even more preferably less than 7 m?·cm2. In yet another embodiment, the semiconductor device has a blocking voltage of at least 20 kV and an on-resistance of less than 20 m?·cm2 and even more preferably less than 10 m?·cm2. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), or a PIN diode.Type: ApplicationFiled: February 6, 2012Publication date: January 31, 2013Applicant: CREE, INC.Inventors: Lin Cheng, Anant K. Agarwal, Michael John O'Loughlin, Albert Augustus Burk, JR., John Williams Palmour
-
Publication number: 20120329216Abstract: Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.Type: ApplicationFiled: September 9, 2011Publication date: December 27, 2012Applicant: CREE, INC.Inventors: Sarit Dhar, Lin Cheng, Sei-Hyung Ryu, Anant Agarwal, John Williams Palmour, Erik Maki, Jason Gurganus, Daniel Jenner Lichtenwalner
-
Publication number: 20120326163Abstract: Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.Type: ApplicationFiled: September 9, 2011Publication date: December 27, 2012Applicant: CREE, INC.Inventors: Sarit Dhar, Lin Cheng, Sei-Hyung Ryu, Anant Agarwal, John Williams Palmour, Jason Gurganus
-
Patent number: 7332795Abstract: A semiconductor device is disclosed that includes a layer of Group III nitride semiconductor material that includes at least one surface, a control contact on the surface for controlling the electrical response of the semiconductor material, a dielectric barrier layer covering at least a portion of the one surface adjacent the control contact, the dielectric barrier layer having a bandgap greater than the bandgap of the Group III nitride and a conduction band offset from the conduction band of the Group III nitride; and a dielectric protective layer covering the remainder of the Group III nitride surface.Type: GrantFiled: May 22, 2004Date of Patent: February 19, 2008Assignee: Cree, Inc.Inventors: Richard Peter Smith, Scott T. Sheppard, John Williams Palmour
-
Publication number: 20030201459Abstract: A high electron mobility transistor (HEMT) is disclosed that includes a semi-insulating silicon carbide substrate, an aluminum nitride buffer layer on the substrate, an insulating gallium nitride layer on the buffer layer, an active structure of aluminum gallium nitride on the gallium nitride layer, a passivation layer on the aluminum gallium nitride active structure, and respective source, drain and gate contacts to the aluminum gallium nitride active structure.Type: ApplicationFiled: May 19, 2003Publication date: October 30, 2003Inventors: Scott Thomas Sheppard, Scott Thomas Allen, John Williams Palmour
-
Patent number: 6583454Abstract: A high electron mobility transistor (HEMT) is disclosed that includes a semi-insulating silicon carbide substrate, an aluminum nitride buffer layer on the substrate, an insulating gallium nitride layer on the buffer layer, an active structure of aluminum gallium nitride on the gallium nitride layer, a passivation layer on the aluminum gallium nitride active structure, and respective source, drain and gate contacts to the aluminum gallium nitride active structure.Type: GrantFiled: March 29, 2001Date of Patent: June 24, 2003Assignee: Cree, Inc.Inventors: Scott Thomas Sheppard, Scott Thomas Allen, John Williams Palmour
-
Patent number: 6486502Abstract: A high electron mobility transistor (HEMT) (10) is disclosed that includes a semi-insulating silicon carbide substrate (11), an aluminum nitride buffer layer (12) on the substrate, an insulating gallium nitride layer (13) on the buffer layer, an active structure of aluminum gallium nitride (14) on the gallium nitride layer, a passivation layer (23) on the aluminum gallium nitride active structure, and respective source, drain and gate contacts (21, 22, 23) to the aluminum gallium nitride active structure.Type: GrantFiled: February 16, 2001Date of Patent: November 26, 2002Assignee: Cree, Inc.Inventors: Scott Thomas Sheppard, Scott Thomas Allen, John Williams Palmour
-
Patent number: 6316793Abstract: A high electron mobility transistor (HEMT) is disclosed that includes a semi-insulating silicon carbide substrate, an aluminum nitride buffer layer on the substrate, an insulating gallium nitride layer on the buffer layer, an active structure of aluminum gallium nitride on the gallium nitride layer, a passivation layer on the aluminum gallium nitride active structure, and respective source, drain and gate contacts to the aluminum gallium nitride active structure.Type: GrantFiled: June 12, 1998Date of Patent: November 13, 2001Assignee: Cree, Inc.Inventors: Scott Thomas Sheppard, Scott Thomas Allen, John Williams Palmour
-
Publication number: 20010017370Abstract: A high electron mobility transistor (HEMT) is disclosed that includes a semi-insulating silicon carbide substrate, an aluminum nitride buffer layer on the substrate, an insulating gallium nitride layer on the buffer layer, an active structure of aluminum gallium nitride on the gallium nitride layer, a passivation layer on the aluminum gallium nitride active structure, and respective source, drain and gate contacts to the aluminum gallium nitride active structure.Type: ApplicationFiled: March 29, 2001Publication date: August 30, 2001Inventors: Scott Thomas Sheppard, Scott Thomas Allen, John Williams Palmour
-
Patent number: 6246076Abstract: A dielectric structure is disclosed for silicon carbide-based semiconductor devices. In gated devices, the structure includes a layer of silicon carbide, a layer of silicon dioxide on the silicon carbide layer, a layer of another insulating material on the silicon dioxide layer, with the insulating material having a dielectric constant higher than the dielectric constant of silicon dioxide, and a gate contact to the insulating material. In other devices the dielectric structure forms an enhanced passivation layer or field insulator.Type: GrantFiled: August 28, 1998Date of Patent: June 12, 2001Assignee: Cree, Inc.Inventors: Lori A. Lipkin, John Williams Palmour
-
Patent number: 5963791Abstract: A SiC MOSFET having a self-aligned gate structure is fabricated upon a monocrystalline substrate layer, such as a p type conductivity .alpha.6H silicon carbide (SiC) substrate. An SiC n+ type conductivity layer is epitaxially grown on the substrate layer. A steep-walled groove is etched through the n+ SiC layer and partially into the p SiC layer at a location on the substrate where a MOSFET gate structure is desired. Subsequently, a thin layer of silicon dioxide and a layer of gate metal are successively deposited over the entire structure. The gate metal layer is deposited with sufficient thickness to substantially fill the groove. A layer of photoresist is applied to the entire surface of the gate metal layer. The photoresist and the underlying gate metal are then reactive ion etched down to the oxide layer, leaving gate metal remaining only in the groove.Type: GrantFiled: July 25, 1997Date of Patent: October 5, 1999Assignee: General Electric CompanyInventors: Dale Marius Brown, Richard Joseph Saia, John Adam Edmond, John Williams Palmour