Patents by Inventor Jong-Soo Yoon
Jong-Soo Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080035971Abstract: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched.Type: ApplicationFiled: May 18, 2007Publication date: February 14, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Mun-Pyo HONG, Woon-Yong PARK, Jong-Soo YOON
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Patent number: 7265799Abstract: A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.Type: GrantFiled: January 16, 2004Date of Patent: September 4, 2007Assignee: Samsung Electronics Co., LtdInventors: Jun-Hyung Souk, Jeong-Young Lee, Jong-Soo Yoon, Kwon-Young Choi, Bum-Ki Baek
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Publication number: 20070200981Abstract: A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.Type: ApplicationFiled: April 27, 2007Publication date: August 30, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun-Hyung SOUK, Jeong-Young Lee, Jong-Soo Yoon, Kwon-Young Choi, Bum-Ki Baek
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Publication number: 20070190706Abstract: A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.Type: ApplicationFiled: March 23, 2007Publication date: August 16, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun-Hyung Souk, Jeong-Young Lee, Jong-Soo Yoon, Kwon-Young Choi, Bum-Ki Baek
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Publication number: 20070126005Abstract: A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad.Type: ApplicationFiled: January 22, 2007Publication date: June 7, 2007Inventors: Bum-Ki Baek, Mun-Pyo Hong, Jang-Soo Kim, Sung-Wook Huh, Jong-Soo Yoon, Doug-Gyu Kim
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Patent number: 7176496Abstract: A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad. Next, a passivation layer is deposited and patterned to form contact holes respectively exposing the drain electrode, the gate pad, and the data pad.Type: GrantFiled: March 16, 2005Date of Patent: February 13, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Bum-Ki Baek, Mun-Pyo Hong, Jang-Soo Kim, Sung-Wook Hao, Jong-Soo Yoon, Dong-Gyu Kim
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Publication number: 20060252168Abstract: A gate conductor including a gate line, a gate pad and a gate electrode is formed on a substrate. A gate insulating layer, a semiconductor layer, a doped amorphous silicon layer and a conductive layer are deposited in sequence, and then a photoresist film pattern is formed thereon. The photoresist film pattern includes a first portion positioned between the to be formed source electrode and drain electrode, a second portion thicker than the first portion, and the third portion with no photoresist. A data conductor including a data line, a data pad, a source electrode, a drain electrode and a conductor pattern for a storage capacitor, an ohmic contact layer pattern and a semiconductor pattern are formed by etching the conductive layer, the doped amorphous silicon layer and the semiconductor layer using the photoresist film pattern. A plurality of color filters of red, green and blue having apertures exposing part of the drain electrode are formed thereon.Type: ApplicationFiled: July 12, 2006Publication date: November 9, 2006Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Joon Rhee, Jong-Soo Yoon
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Publication number: 20060228821Abstract: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched.Type: ApplicationFiled: June 13, 2006Publication date: October 12, 2006Inventors: Mun-Pyo Hong, Woon-Yong Park, Jong-Soo Yoon
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Patent number: 7102168Abstract: A gate wire including a gate line, a gate pad and a gate electrode is formed on a substrate. A gate insulating layer, a semiconductor layer, a doped amorphous silicon layer and a conductive layer are deposited in sequence, and then a photoresist film pattern is formed thereon. The photoresist film pattern includes a first portion positioned between a source electrode and a drain electrode, a second portion thicker than the first portion, and the third portion with no photoresist. A data wire including a data line, a data pad, a source electrode, a drain electrode and a conductor pattern for storage capacitor, an ohmic contact layer pattern and a semiconductor pattern are formed by etching the conductive layer, the doped amorphous silicon layer and the semiconductor layer using the photoresist film pattern. A plurality of color filters of red, green and blue having apertures exposing part of the drain electrode are formed thereon.Type: GrantFiled: December 23, 2002Date of Patent: September 5, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Joon Rhee, Jong-Soo Yoon
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Publication number: 20060192747Abstract: In an LCD apparatus (400) having simplified structure and improved luminance, a light supplying unit (100) supplies an LCD panel (280) with red light during a time corresponding to one-third of a frame, green light during the time and blue light during the time. A light reflective-transmissive unit is disposed between the light supplying unit (100) and the LCD panel assembly (200) to transmit the red light, the green light and the blue light and to reflect an external light from exterior of the LCD panel assembly (200). The LCD apparatus displays an image by means of white light as well as red light, green light and blue light, thereby improving luminance and simplifying structure.Type: ApplicationFiled: March 16, 2004Publication date: August 31, 2006Inventors: Jong-Soo Yoon, Dong-Ho Lee
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Patent number: 7098480Abstract: Disclosed is a simplified method for manufacturing a liquid crystal display. A gate wire including a gate line, a gate pad, and a gate electrode are formed on a substrate. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially deposited, and a photoresist layer is coated thereon. The photoresist layer is exposed to light through a mask and developed to form a photoresist pattern. At this time, a first portion of the photoresist pattern which is located between the source electrode and the drain electrode is thinner than a second portion which is located on the data wire, and the photoresist layer is totally removed on other parts. The thin portion is made by controlling the amount of irradiating light or by a reflow process to form a thin portion, and the amount of light is controlled by using a mask that has a slit, a small pattern smaller than the resolution of the exposure device, or a partially transparent layer.Type: GrantFiled: October 18, 2002Date of Patent: August 29, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Gyu Kim, Jong-Soo Yoon
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Publication number: 20060157712Abstract: Disclosed is a simplified method for manufacturing a liquid crystal display. A gate wire including a gate line, a gate pad, and a gate electrode are formed on a substrate. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially deposited, and a photoresist layer is coated thereon. The photoresist layer is exposed to light through a mask and developed to form a photoresist pattern. At this time, a first portion of the photoresist pattern which is located between the source electrode and the drain electrode is thinner than a second portion which is located on the data wire, and the photoresist layer is totally removed on other parts. The thin portion is made by controlling the amount of irradiating light or by a reflow process to form a thin portion, and the amount of light is controlled by using a mask that has a slit, a small pattern smaller than the resolution of the exposure device, or a partially transparent layer.Type: ApplicationFiled: March 16, 2006Publication date: July 20, 2006Inventors: Dong-Gyu Kim, Jong-Soo Yoon
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Patent number: 7078255Abstract: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched.Type: GrantFiled: September 3, 2004Date of Patent: July 18, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Mun-Pyo Hong, Woon-Yong Park, Jong-Soo Yoon
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Patent number: 6937303Abstract: Disclosed is a transmissive and reflective type LCD. In the LCD, a second substrate faces a first substrate. Liquid crystal layer is formed between the first and second substrate. A first polarizing plate is formed on outer surface of the first substrate. A second polarizing plate is formed on outer surface of the second substrate. A backlight is arranged at a rear side of the first polarizing plate. A transparent transflective film is arranged between the first polarizing plate and the backlight and has a plurality of layers where a first and a second layer each having different refractivity indexes are alternatively stacked. The transparent transflective film partially reflects and transmits incident light. By a restoring process occurring between the transflective film and the backlight, a predetermined amount of the incident light is transmitted through the transflective film repeatedly, so that transmissivity and light efficiency are enhanced.Type: GrantFiled: December 18, 2002Date of Patent: August 30, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Kyu Jang, Hyung-Guel Kim, Jong-Soo Yoon, Dong-Ho Lee
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Publication number: 20050170592Abstract: A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad. Next, a passivation layer is deposited and patterned to form contact holes respectively exposing the drain electrode, the gate pad, and the data pad.Type: ApplicationFiled: March 16, 2005Publication date: August 4, 2005Inventors: Bum-Ki Baek, Mun-Pyo Hong, Jang-Soo Kim, Sung-Wook Huh, Jong-Soo Yoon, Dong-Gyu Kim
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Patent number: 6887742Abstract: A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad. Next, a passivation layer is deposited and patterned to form contact holes respectively exposing the drain electrode, the gate pad, and the data pad.Type: GrantFiled: November 25, 2002Date of Patent: May 3, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Bum-Ki Baek, Mun-Pyo Hong, Jang-Soo Kim, Sung-Wook Huh, Jong-Soo Yoon, Dong-Gyu Kim
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Publication number: 20050082536Abstract: The invention is directed to simultaneously etching thin films to different uniform depths depending on positions by using a photoresist pattern having different thickness depending on positions as an etch mask in order to form a contact hole for a gate pad along with at least one other layer, or a data wire and a semiconductor pattern, via a single photolithography step.Type: ApplicationFiled: September 3, 2004Publication date: April 21, 2005Inventors: Woon-Yong Park, Jong-Soo Yoon
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Publication number: 20050023534Abstract: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched.Type: ApplicationFiled: September 3, 2004Publication date: February 3, 2005Inventors: Mun-Pyo Hong, Woon-Yong Park, Jong-Soo Yoon
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Patent number: 6849873Abstract: In liquid crystal display device having a multi-layer conductive layer, such conductive layer is formed using a photoresist pattern having different thicknesses depending on the position. Upper layer of the gate pad is removed using an etch mask of the photoresist pattern of different thickness. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire. Finally passivation layer is formed and an indium tin oxide layer is deposited and patterned to form a pixel electrode, a redundant gate pad, and a redundant data pad.Type: GrantFiled: November 25, 2002Date of Patent: February 1, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Bum-Ki Baek, Mun-Pyo Hong, Jang-Soo Kim, Sung-Wook Huh, Jong-Soo Yoon, Dong-Gyu Kim
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Patent number: RE40162Abstract: A thin film transistor substrate for a liquid crystal display includes an insulating substrate, and a gate line assembly formed on the substrate. The gate line assembly has a double-layered structure with a lower layer exhibiting good contact characteristics with respect to indium tin oxide, and an upper layer exhibiting low resistance characteristics. A gate insulating layer, a semiconductor layer, a contact layer, and first and second data line layers are sequentially deposited onto the substrate with the gate line assembly. The first and second data line layers are patterned to form a data line assembly, and the contact layer is etched through the pattern of the data line assembly such that the contact layer has the same pattern as the data line assembly. A passivation layer is deposited onto the data line assembly, and a photoresist pattern is formed on the passivation layer by using a mask of different light transmissties mainly at a display area and a peripheral area.Type: GrantFiled: December 31, 2003Date of Patent: March 25, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Woon-Yong Park, Jong-Soo Yoon, Chang-Oh Jeong