Patents by Inventor Jong-Youn Kim
Jong-Youn Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162549Abstract: The battery pack includes a battery module; a processing unit which is electrically connected to the battery module and configured to control charge/discharge of the battery module, wherein at least one of the battery module or the processing unit is configured to allow another battery module or another processing unit to be coupled to two or more sides thereof.Type: ApplicationFiled: December 21, 2022Publication date: May 16, 2024Applicant: LG ENERGY SOLUTION, LTD.Inventors: Byung-Hyuk CHOI, Jong-Chan SHIN, Ki-Youn KIM
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Patent number: 11978829Abstract: A display device including a circuit board, and pixels each including a light emitting structure including epitaxial stacks and having a light emitting area defined by the epitaxial stacks, an encapsulating member covering a side surface and an upper surface of the light emitting structure, bump electrodes disposed on the light emitting structure, at least a portion of each bump electrode overlapping with the light emitting area, and fan-out lines disposed on the encapsulating member and electrically connected to the light emitting structure through the bump electrodes, in which at least a first portion of a surface of the fan-out lines is exposed to the outside to receive electrical signal for independent driving of the light emitting structure, and the first portion of the fan-out lines does not overlap the light emitting area in a plan view.Type: GrantFiled: November 3, 2022Date of Patent: May 7, 2024Assignee: SEOUL VIOSYS CO., LTD.Inventors: Jong Min Jang, Chang Youn Kim
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Patent number: 11967549Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces opposed to each other, and including an insulation member, a plurality of redistribution layers on different levels in the insulation member, and a redistribution via having a shape narrowing from the second surface toward the first surface in a first direction; a plurality of UBM layers, each including a UBM pad on the first surface of the redistribution substrate, and a UBM via having a shape narrowing in a second direction, opposite to the first direction; and at least one semiconductor chip on the second surface of the redistribution substrate, and having a plurality of contact pads electrically connected to the redistribution layer adjacent to the second surface among the plurality of redistribution layers.Type: GrantFiled: October 24, 2021Date of Patent: April 23, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Ho Park, Jong Youn Kim, Min Jun Bae
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Publication number: 20240099665Abstract: The embodiments disclosed herein provide an electrocardiogram data processing server, an electrocardiogram data processing method, and a computer program. The embodiments disclosed herein further provide an electrocardiogram data processing server, an electrocardiogram data processing method, and a computer program, the electrocardiogram data processing server configured to determine whether analysis is required while segmenting an electrocardiogram signal into signal segments with variable window sizes, for instance, by changing a window size of a signal segment according to whether analysis of a previous signal segment is required.Type: ApplicationFiled: September 25, 2023Publication date: March 28, 2024Applicant: ATSENS CO., LTD.Inventors: Kab Mun CHA, Tae Youn KIM, Byung Jin MOON, Jong Ook JEONG
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Publication number: 20240097238Abstract: A battery pack is advantageous for effective control and maintenance of thermal events. A battery pack according to one aspect of the present disclosure may include a battery module having one or more battery cells; a fire extinguishing tank holding a fire extinguishing liquid, disposed on top of the battery module and having a through hole formed therein; and a cover member installed in the through hole of the fire extinguishing tank and configured to open or close the through hole according to a change in internal pressure of the fire extinguishing tank.Type: ApplicationFiled: December 20, 2022Publication date: March 21, 2024Applicant: LG ENERGY SOLUTION, LTD.Inventors: Jong-Kyu AHN, Ki-Youn KIM, Hyeon-Kyu KIM, Jeong-O MUN, Gi-Dong PARK, Young-Won YUN, Seong-Ju LEE, Jae-Ki LEE
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Patent number: 11935990Abstract: A light emitting diode including a side reflection layer. The light emitting diode includes: a semiconductor stack and a light exit surface having a roughened surface through which light generated from an active layer is emitted; side surfaces defining the light exit surface; and a side reflection layer covering at least part of the side surfaces. The light exit surface is disposed over a first conductivity type semiconductor layer opposite to the ohmic reflection layer, all layers from the active layer to the light exit surface are formed of gallium nitride-based semiconductors, and a distance from the active layer to the light exit surface is 50 ?m or more.Type: GrantFiled: November 29, 2021Date of Patent: March 19, 2024Assignee: Seoul Viosys Co., Ltd.Inventors: Jong Min Jang, Chae Hon Kim, Chang Youn Kim, Jae Hee Lim
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Publication number: 20240079388Abstract: A light module including a base substrate having a front surface, first and second electrodes disposed on the front surface, first and second emitters disposed on the front surface, a first molding covering the first emitter, and a second molding layer covering the second emitter, in which the first and second electrodes include a first region and a second region exposed from the base substrate, and an embedded region between the first region and the second region and not exposed to the outside, and a distance between the second region of the first electrode is connected to the first emitter and the second region of the second electrode connected to the second emitter is shorter than a distance between the first region of the first electrode connected to the first emitter and the first region of the second electrode connected the second emitter.Type: ApplicationFiled: October 30, 2023Publication date: March 7, 2024Inventors: Jong Min JANG, Chang Youn KIM
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Publication number: 20240014163Abstract: A semiconductor package includes a redistribution substrate having a first side and an opposite second side, a semiconductor chip on the first side of the redistribution substrate, a silicon capacitor on the second side of the redistribution substrate, a plurality of solder balls on the second side of the redistribution substrate and adjacent the silicon capacitor, and a metal pattern in the redistribution substrate and positioned between the silicon capacitor and the solder balls. The metal pattern includes a first portion extending in a first direction, and a second portion connected to the first portion and extending in a second direction different from the first direction.Type: ApplicationFiled: May 4, 2023Publication date: January 11, 2024Inventors: Jong Youn KIM, Eung Kyu KIM, Min Jun BAE, Hyeon Seok LEE, Seok Kyu CHOI
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Publication number: 20230317623Abstract: Provided is a semiconductor package including an interposer. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; at least one interposer including a plurality of first connection pillars spaced apart from each other on the lower redistribution line structure and connected respectively to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns connected respectively to the plurality of first connection pillars and the plurality of connection wiring patterns, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips adhered on the upper redistribution line structure while being spaced apart from each other.Type: ApplicationFiled: June 9, 2023Publication date: October 5, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Jong-youn KIM, Seok-hyun LEE
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Patent number: 11710701Abstract: Provided is a semiconductor package including an interposer. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; at least one interposer including a plurality of first connection pillars spaced apart from each other on the lower redistribution line structure and connected respectively to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns connected respectively to the plurality of first connection pillars and the plurality of connection wiring patterns, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips adhered on the upper redistribution line structure while being spaced apart from each other.Type: GrantFiled: May 13, 2022Date of Patent: July 25, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-youn Kim, Seok-hyun Lee
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Publication number: 20220352050Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip on a substrate, a barrier layer on the first semiconductor chip and the second semiconductor chip, the barrier layer having an opening through which at least a part of the first semiconductor chip is exposed, and a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.Type: ApplicationFiled: July 18, 2022Publication date: November 3, 2022Inventors: Dong Kyu KIM, Jung-Ho PARK, Jong Youn KIM, Yeon Ho JANG, Jae Gwon JANG
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Patent number: 11462464Abstract: A fan-out semiconductor package including a redistribution line structure is provided. The fan-out semiconductor package includes a plurality of redistribution line insulating layers and a plurality of redistribution line patterns arranged on at least one of an upper surface and a lower surface of each of the plurality of redistribution line insulating layers; at least one semiconductor chip arranged on the redistribution line structure and occupying a footprint having a horizontal width that is less than a horizontal width of the redistribution line structure; and a molding member surrounding the at least one semiconductor chip on the redistribution line structure and having a horizontal width that is greater than the horizontal width of the redistribution line structure, wherein the plurality of redistribution line insulating layers have a cascade structure.Type: GrantFiled: December 3, 2020Date of Patent: October 4, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-youn Kim, Seok-hyun Lee
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Publication number: 20220270975Abstract: Provided is a semiconductor package including an interposer. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; at least one interposer including a plurality of first connection pillars spaced apart from each other on the lower redistribution line structure and connected respectively to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns connected respectively to the plurality of first connection pillars and the plurality of connection wiring patterns, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips adhered on the upper redistribution line structure while being spaced apart from each other.Type: ApplicationFiled: May 13, 2022Publication date: August 25, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Jong-youn KIM, Seok-hyun LEE
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Patent number: 11404346Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip on a substrate, a barrier layer on the first semiconductor chip and the second semiconductor chip, the barrier layer having an opening through which at least a part of the first semiconductor chip is exposed, and a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.Type: GrantFiled: January 15, 2020Date of Patent: August 2, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Dong Kyu Kim, Jung-Ho Park, Jong Youn Kim, Yeon Ho Jang, Jae Gwon Jang
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Patent number: 11373980Abstract: A semiconductor package includes a first semiconductor chip including a first surface and a second surface which face each other, an alignment pattern formed on the first surface, a first redistribution layer arranged on the first surface of the first semiconductor chip, a second redistribution layer arranged on the second surface of the first semiconductor chip, and electrically connected with the semiconductor chip, and a first dielectric layer including the alignment pattern between the first redistribution layer and the semiconductor chip, the alignment pattern overlapping the first surface of the first semiconductor chip.Type: GrantFiled: January 16, 2020Date of Patent: June 28, 2022Assignee: Samsung Electronics Co, Ltd.Inventors: Jong Youn Kim, Dong Kyu Kim, Jin-Woo Park, Min Jun Bae, Gwang Jae Jeon
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Patent number: 11355440Abstract: Provided is a semiconductor package including an interposer. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; at least one interposer including a plurality of first connection pillars spaced apart from each other on the lower redistribution line structure and connected respectively to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns connected respectively to the plurality of first connection pillars and the plurality of connection wiring patterns, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips adhered on the upper redistribution line structure while being spaced apart from each other.Type: GrantFiled: November 20, 2020Date of Patent: June 7, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-youn Kim, Seok-hyun Lee
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Publication number: 20220044992Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces opposed to each other, and including an insulation member, a plurality of redistribution layers on different levels in the insulation member, and a redistribution via having a shape narrowing from the second surface toward the first surface in a first direction; a plurality of UBM layers, each including a UBM pad on the first surface of the redistribution substrate, and a UBM via having a shape narrowing in a second direction, opposite to the first direction; and at least one semiconductor chip on the second surface of the redistribution substrate, and having a plurality of contact pads electrically connected to the redistribution layer adjacent to the second surface among the plurality of redistribution layers.Type: ApplicationFiled: October 24, 2021Publication date: February 10, 2022Inventors: Jung Ho PARK, Jong Youn KIM, Min Jun BAE
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Patent number: 11177205Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces opposed to each other, and including an insulation member, a plurality of redistribution layers on different levels in the insulation member, and a redistribution via having a shape narrowing from the second surface toward the first surface in a first direction; a plurality of UBM layers, each including a UBM pad on the first surface of the redistribution substrate, and a UBM via having a shape narrowing in a second direction, opposite to the first direction; and at least one semiconductor chip on the second surface of the redistribution substrate, and having a plurality of contact pads electrically connected to the redistribution layer adjacent to the second surface among the plurality of redistribution layers.Type: GrantFiled: June 27, 2019Date of Patent: November 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Ho Park, Jong Youn Kim, Min Jun Bae
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Patent number: 11101231Abstract: Provided is a semiconductor package including a semiconductor chip, a molding portion surrounding at least a side surface of the semiconductor chip, a passivation layer including a contact plug connected to the semiconductor chip and having a narrowing width further away from the semiconductor chip in a vertical direction, below the semiconductor chip, and a redistribution layer portion electrically connecting the semiconductor chip with an external connection terminal, below the passivation layer. The redistribution layer portion includes an upper pad connected to the contact plug and a fine pattern positioned at a same level as the upper pad, a redistribution layer and a via plug, which has a widening width further away from the semiconductor chip in the vertical direction, and a lower pad connected to the external connection terminal and exposed to an outside of the semiconductor package in a lower part of the redistribution layer portion.Type: GrantFiled: March 16, 2020Date of Patent: August 24, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-youn Kim, Seok-hyun Lee, Youn-ji Min, Kyoung-lim Suk, Seok-won Lee
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Publication number: 20210090986Abstract: A fan-out semiconductor package including a redistribution line structure is provided. The fan-out semiconductor package includes a plurality of redistribution line insulating layers and a plurality of redistribution line patterns arranged on at least one of an upper surface and a lower surface of each of the plurality of redistribution line insulating layers; at least one semiconductor chip arranged on the redistribution line structure and occupying a footprint having a horizontal width that is less than a horizontal width of the redistribution line structure; and a molding member surrounding the at least one semiconductor chip on the redistribution line structure and having a horizontal width that is greater than the horizontal width of the redistribution line structure, wherein the plurality of redistribution line insulating layers have a cascade structure.Type: ApplicationFiled: December 3, 2020Publication date: March 25, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Jong-youn KIM, Seok-hyun LEE