Patents by Inventor Jong-Youn Kim
Jong-Youn Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220044992Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces opposed to each other, and including an insulation member, a plurality of redistribution layers on different levels in the insulation member, and a redistribution via having a shape narrowing from the second surface toward the first surface in a first direction; a plurality of UBM layers, each including a UBM pad on the first surface of the redistribution substrate, and a UBM via having a shape narrowing in a second direction, opposite to the first direction; and at least one semiconductor chip on the second surface of the redistribution substrate, and having a plurality of contact pads electrically connected to the redistribution layer adjacent to the second surface among the plurality of redistribution layers.Type: ApplicationFiled: October 24, 2021Publication date: February 10, 2022Inventors: Jung Ho PARK, Jong Youn KIM, Min Jun BAE
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Patent number: 11177205Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces opposed to each other, and including an insulation member, a plurality of redistribution layers on different levels in the insulation member, and a redistribution via having a shape narrowing from the second surface toward the first surface in a first direction; a plurality of UBM layers, each including a UBM pad on the first surface of the redistribution substrate, and a UBM via having a shape narrowing in a second direction, opposite to the first direction; and at least one semiconductor chip on the second surface of the redistribution substrate, and having a plurality of contact pads electrically connected to the redistribution layer adjacent to the second surface among the plurality of redistribution layers.Type: GrantFiled: June 27, 2019Date of Patent: November 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Ho Park, Jong Youn Kim, Min Jun Bae
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Patent number: 11101231Abstract: Provided is a semiconductor package including a semiconductor chip, a molding portion surrounding at least a side surface of the semiconductor chip, a passivation layer including a contact plug connected to the semiconductor chip and having a narrowing width further away from the semiconductor chip in a vertical direction, below the semiconductor chip, and a redistribution layer portion electrically connecting the semiconductor chip with an external connection terminal, below the passivation layer. The redistribution layer portion includes an upper pad connected to the contact plug and a fine pattern positioned at a same level as the upper pad, a redistribution layer and a via plug, which has a widening width further away from the semiconductor chip in the vertical direction, and a lower pad connected to the external connection terminal and exposed to an outside of the semiconductor package in a lower part of the redistribution layer portion.Type: GrantFiled: March 16, 2020Date of Patent: August 24, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-youn Kim, Seok-hyun Lee, Youn-ji Min, Kyoung-lim Suk, Seok-won Lee
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Publication number: 20210090986Abstract: A fan-out semiconductor package including a redistribution line structure is provided. The fan-out semiconductor package includes a plurality of redistribution line insulating layers and a plurality of redistribution line patterns arranged on at least one of an upper surface and a lower surface of each of the plurality of redistribution line insulating layers; at least one semiconductor chip arranged on the redistribution line structure and occupying a footprint having a horizontal width that is less than a horizontal width of the redistribution line structure; and a molding member surrounding the at least one semiconductor chip on the redistribution line structure and having a horizontal width that is greater than the horizontal width of the redistribution line structure, wherein the plurality of redistribution line insulating layers have a cascade structure.Type: ApplicationFiled: December 3, 2020Publication date: March 25, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Jong-youn KIM, Seok-hyun LEE
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Publication number: 20210074646Abstract: Provided is a semiconductor package including an interposer. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; at least one interposer including a plurality of first connection pillars spaced apart from each other on the lower redistribution line structure and connected respectively to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns connected respectively to the plurality of first connection pillars and the plurality of connection wiring patterns, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips adhered on the upper redistribution line structure while being spaced apart from each other.Type: ApplicationFiled: November 20, 2020Publication date: March 11, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Jong-youn KIM, Seok-hyun LEE
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Publication number: 20210020608Abstract: A semiconductor package includes a first semiconductor chip including a first surface and a second surface which face each other, an alignment pattern formed on the first surface, a first redistribution layer arranged on the first surface of the first semiconductor chip, a second redistribution layer arranged on the second surface of the first semiconductor chip, and electrically connected with the semiconductor chip, and a first dielectric layer including the alignment pattern between the first redistribution layer and the semiconductor chip, the alignment pattern overlapping the first surface of the first semiconductor chip.Type: ApplicationFiled: January 16, 2020Publication date: January 21, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Jong Youn KIM, Dong Kyu Kim, Jin-Woo Park, Min Jun Bae, Gwang Jae Jeon
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Publication number: 20200411405Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip on a substrate, a barrier layer on the first semiconductor chip and the second semiconductor chip, the barrier layer having an opening through which at least a part of the first semiconductor chip is exposed, and a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.Type: ApplicationFiled: January 15, 2020Publication date: December 31, 2020Inventors: Dong Kyu KIM, Jung-Ho PARK, Jong Youn KIM, Yeon Ho JANG, Jae Gwon JANG
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Patent number: 10879163Abstract: A fan-out semiconductor package including a redistribution line structure is provided. The fan-out semiconductor package includes a plurality of redistribution line insulating layers and a plurality of redistribution line patterns arranged on at least one of an upper surface and a lower surface of each of the plurality of redistribution line insulating layers; at least one semiconductor chip arranged on the redistribution line structure and occupying a footprint having a horizontal width that is less than a horizontal width of the redistribution line structure; and a molding member surrounding the at least one semiconductor chip on the redistribution line structure and having a horizontal width that is greater than the horizontal width of the redistribution line structure, wherein the plurality of redistribution line insulating layers have a cascade structure.Type: GrantFiled: March 12, 2019Date of Patent: December 29, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Youn Kim, Seok-Hyun Lee
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Patent number: 10847468Abstract: Provided is a semiconductor package including an interposer. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; at least one interposer including a plurality of first connection pillars spaced apart from each other on the lower redistribution line structure and connected respectively to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns connected respectively to the plurality of first connection pillars and the plurality of connection wiring patterns, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips adhered on the upper redistribution line structure while being spaced apart from each other.Type: GrantFiled: March 12, 2019Date of Patent: November 24, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-youn Kim, Seok-hyun Lee
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Publication number: 20200219834Abstract: Provided is a semiconductor package including a semiconductor chip, a molding portion surrounding at least a side surface of the semiconductor chip, a passivation layer including a contact plug connected to the semiconductor chip and having a narrowing width further away from the semiconductor chip in a vertical direction, below the semiconductor chip, and a redistribution layer portion electrically connecting the semiconductor chip with an external connection terminal, below the passivation layer. The redistribution layer portion includes an upper pad connected to the contact plug and a fine pattern positioned at a same level as the upper pad, a redistribution layer and a via plug, which has a widening width further away from the semiconductor chip in the vertical direction, and a lower pad connected to the external connection terminal and exposed to an outside of the semiconductor package in a lower part of the redistribution layer portion.Type: ApplicationFiled: March 16, 2020Publication date: July 9, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-youn KIM, Seok-hyun Lee, Youn-ji Min, Kyoung-lim Suk, Seok-won Lee
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Publication number: 20200194362Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces opposed to each other, and including an insulation member, a plurality of redistribution layers on different levels in the insulation member, and a redistribution via having a shape narrowing from the second surface toward the first surface in a first direction; a plurality of UBM layers, each including a UBM pad on the first surface of the redistribution substrate, and a UBM via having a shape narrowing in a second direction, opposite to the first direction; and at least one semiconductor chip on the second surface of the redistribution substrate, and having a plurality of contact pads electrically connected to the redistribution layer adjacent to the second surface among the plurality of redistribution layers.Type: ApplicationFiled: June 27, 2019Publication date: June 18, 2020Inventors: Jung Ho PARK, Jong Youn KIM, Min Jun BAE
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Patent number: 10622320Abstract: A semiconductor package may include a semiconductor chip; a molding portion configured to surround at least a side surface of the semiconductor chip; a passivation layer including a contact plug connected to the semiconductor chip and having a narrowing width further away from the semiconductor chip in a vertical direction, below the semiconductor chip; and a redistribution layer portion electrically connecting the semiconductor chip with an external connection terminal, below the passivation layer.Type: GrantFiled: January 12, 2018Date of Patent: April 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-youn Kim, Seok-hyun Lee, Youn-ji Min, Kyoung-lim Suk, Seok-won Lee
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Publication number: 20200043840Abstract: A fan-out semiconductor package including a redistribution line structure is provided. The fan-out semiconductor package includes a plurality of redistribution line insulating layers and a plurality of redistribution line patterns arranged on at least one of an upper surface and a lower surface of each of the plurality of redistribution line insulating layers; at least one semiconductor chip arranged on the redistribution line structure and occupying a footprint having a horizontal width that is less than a horizontal width of the redistribution line structure; and a molding member surrounding the at least one semiconductor chip on the redistribution line structure and having a horizontal width that is greater than the horizontal width of the redistribution line structure, wherein the plurality of redistribution line insulating layers have a cascade structure.Type: ApplicationFiled: March 12, 2019Publication date: February 6, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Jong-youn Kim, Seok-hyun Lee
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Publication number: 20200043853Abstract: Provided is a semiconductor package including an interposer. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; at least one interposer including a plurality of first connection pillars spaced apart from each other on the lower redistribution line structure and connected respectively to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns connected respectively to the plurality of first connection pillars and the plurality of connection wiring patterns, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips adhered on the upper redistribution line structure while being spaced apart from each other.Type: ApplicationFiled: March 12, 2019Publication date: February 6, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Jong-youn KIM, Seok-hyun Lee
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Publication number: 20190027451Abstract: A semiconductor package may include a semiconductor chip; a molding portion configured to surround at least a side surface of the semiconductor chip; a passivation layer including a contact plug connected to the semiconductor chip and having a narrowing width further away from the semiconductor chip in a vertical direction, below the semiconductor chip; and a redistribution layer portion electrically connecting the semiconductor chip with an external connection terminal, below the passivation layer.Type: ApplicationFiled: January 12, 2018Publication date: January 24, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-youn KIM, Seok-hyun LEE, Youn-ji MIN, Kyoung-lim SUK, Seok-won LEE
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Publication number: 20170098269Abstract: Provided is an artificial intelligence chat method for providing necessary information based on chatting documents.Type: ApplicationFiled: October 20, 2016Publication date: April 6, 2017Inventor: Jong Youn Kim
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Patent number: 9298690Abstract: A method for analyzing emotion based upon a messenger conversation is disclosed herein. The method may include the steps of storing survey information of a user respective to a specific counterpart with whom the user wishes to analyze emotion, opening a conversation history between the user and the specific counterpart, analyzing the survey information and the conversation history, thereby analyzing the emotion between the user and the specific counterpart, and showing the emotion analysis to the user.Type: GrantFiled: January 13, 2014Date of Patent: March 29, 2016Assignee: ScatterLab Inc.Inventor: Jong Youn Kim
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Publication number: 20150186354Abstract: A method for analyzing emotion based upon a messenger conversation is disclosed herein. The method may include the steps of storing survey information of a user respective to a specific counterpart with whom the user wishes to analyze emotion, opening a conversation history between the user and the specific counterpart, analyzing the survey information and the conversation history, thereby analyzing the emotion between the user and the specific counterpart, and showing the emotion analysis to the user.Type: ApplicationFiled: January 13, 2014Publication date: July 2, 2015Applicant: ScatterLab Inc.Inventor: Jong Youn KIM
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Patent number: 9054228Abstract: Semiconductor packages including a heat spreader and methods of forming the same are provided. The semiconductor packages may include a first semiconductor chip, a second semiconductor chip, and a heat spreader stacked sequentially. The semiconductor packages may also include a thermal interface material (TIM) layer surrounding the second semiconductor chip and directly contacting a sidewall of the second semiconductor chip. An upper surface of the TIM layer may directly contact a lower surface of the heat spreader, and a sidewall of the TIM layer may be substantially coplanar with a sidewall of the heat spreader. In some embodiments, a sidewall of the first semiconductor chip may be substantially coplanar with the sidewall of the TIM layer.Type: GrantFiled: January 21, 2014Date of Patent: June 9, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Kyoung Choi, Jong-Youn Kim, Sang-Wook Park, Hae-Jung Yu, In-Young Lee, Sang-Uk Han, Ji-Seok Hong
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Patent number: 8940557Abstract: A method of fabricating a wafer level package includes preparing a wafer including a plurality of first semiconductor chips, mounting a plurality of second semiconductor chips on the wafer, disposing the wafer on a lower mold and disposing an upper mold so as to surround edges of a top surface of the wafer, dispensing a molding member on the wafer, and pressurizing the molding member by using a plunger so as to fabricate a wafer level package in which a top surface of each of the plurality of second semiconductor chips is exposed.Type: GrantFiled: June 19, 2013Date of Patent: January 27, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-won Kim, Jong-youn Kim, Eun-kyoung Choi, Sang-uk Han, Ji-seok Hong