Patents by Inventor Joon Han

Joon Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11688105
    Abstract: A processor implemented method of processing a facial expression image, the method includes controlling a camera to capture a first facial expression image and a second facial expression image, acquiring a first expression feature of the first facial expression image, acquiring a second expression feature of the second facial expression image, generating a new expression feature dependent on differences between the acquired first expression feature and the acquired second expression feature, and adjusting a target facial expression image based on the new expression feature.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: June 27, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tianchu Guo, Youngsung Kim, Hui Zhang, Byungin Yoo, Chang Kyu Choi, Jae-Joon Han, Jingtao Xu, Deheng Qian
  • Publication number: 20230194422
    Abstract: A chemical liquid supply unit includes a chemical liquid storage storing a chemical liquid, a chemical liquid supply line that is connected to the chemical liquid storage, the chemical liquid flowing through the chemical liquid supply line from the chemical liquid storage, and a chemical liquid inspection means detecting impurities from the chemical liquid flowing through the chemical liquid supply line using a spectroscopy method.
    Type: Application
    Filed: December 13, 2022
    Publication date: June 22, 2023
    Applicant: SEMES CO., LTD.
    Inventors: Seung Tae YANG, Sang Woo PARK, Young Joon HAN, Gi Hun CHOI, Moon Soon CHOI, Seong Hyeon KIM, Bu Young JUNG
  • Publication number: 20230185079
    Abstract: A pattern electrode structure, which is stacked between a base material and a dielectric layer of an electro-wetting apparatus, includes a plurality of branch electrodes formed in a direction perpendicular to an arbitrary plane perpendicular to a plane formed by the pattern electrode structure to be spaced from each other at regular intervals, and a plurality of sub-branch electrodes formed to extend from the plurality of branch electrodes by as much as a predetermined length in an inclined direction, whereby, self-cleaning performance may be more efficiently exhibited even for small droplets.
    Type: Application
    Filed: May 18, 2022
    Publication date: June 15, 2023
    Applicants: Hyundai Motor Company, Kia Corporation
    Inventors: Kwang-Joon Han, Jai-Min Han, Byung-Kyu Cho
  • Publication number: 20230182131
    Abstract: A pattern electrode structure for an electrowetting apparatus, which is laminated between a base material and a dielectric layer of the electrowetting apparatus, includes a first electrode portion including a first electrode connection portion, a first basal pattern electrode connected to the first electrode connection portion, and a plurality of first upper branch electrodes connected to the first basal pattern electrode, and a second electrode portion including a second electrode connection portion, a second basal pattern electrode connected to the second electrode connection portion, and a plurality of second upper branch electrodes connected to the second basal pattern electrode, the second electrode portion having a different polarity from the first electrode portion, in which the second basal pattern electrode extends and traverses in a width direction of a plane of the pattern electrode structure.
    Type: Application
    Filed: May 19, 2022
    Publication date: June 15, 2023
    Applicants: Hyundai Motor Company, Kia Corporation
    Inventors: Kwang-Joon HAN, Jai-Min HAN, Byung-Kyu CHO
  • Publication number: 20230176359
    Abstract: A pattern electrode structure stacked between a base material and a dielectric layer of an electro-wetting device includes a center branch electrode extending in a first direction, and a plurality of sub-branch electrodes extending from the center branch electrode in an inclined direction relative to the first direction. According to the present disclosure, self-cleaning performance can be more efficiently exhibited even for small droplets.
    Type: Application
    Filed: May 18, 2022
    Publication date: June 8, 2023
    Applicants: Hyundai Motor Company, Kia Corporation
    Inventors: Byung-Kyu CHO, Jai-Min HAN, Kwang-Joon HAN
  • Publication number: 20230154040
    Abstract: A method and apparatus with landmark coordinate prediction are provided. The method includes generating a multi-stage feature map for landmarks of a face image through a staged convolutional network, generating an initial query matrix by fully connecting a last-stage feature map in the multi-stage feature map using a fully connected network, where a total number of feature elements in the initial query matrix is equal to a total number of predicted landmarks of the face image, generating a memory feature matrix by flattening and connecting the multi-stage feature map, generating the predicted landmark coordinates by inputting the memory feature matrix and the initial query matrix to a decoder network of plural cascaded decoder networks.
    Type: Application
    Filed: November 15, 2022
    Publication date: May 18, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Zidong GUO, Jae-Joon HAN, Seon-Min RHEE, Seungju HAN, Hui LI
  • Publication number: 20230119080
    Abstract: A face verification method and apparatus is disclosed. The face verification method includes selecting a current verification mode, from among plural verification modes, to be implemented for the verifying of the face, determining one or more recognizers, from among plural recognizers, based on the selected current verification mode, extracting feature information from information of the face using at least one of the determined one or more recognizers, and indicating whether a verification is successful based on the extracted feature information.
    Type: Application
    Filed: December 16, 2022
    Publication date: April 20, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Changyong SON, Deoksang KIM, Minsu KO, Jinwoo SON, Seungju HAN, Chang Kyu CHOI, Jae-Joon HAN
  • Patent number: 11625601
    Abstract: A lightened neural network, method, and apparatus, and recognition method and apparatus implementing the same. A neural network includes a plurality of layers each comprising neurons and plural synapses connecting neurons included in neighboring layers. Synaptic weights with values greater than zero and less than a preset value of a variable a, which is greater than zero, may be at least partially set to zero. Synaptic weights with values greater than a preset value of a variable b, which is greater than zero, may be at least partially set to the preset value of the variable b.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: April 11, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changyong Son, Jinwoo Son, Byungin Yoo, Chang Kyu Choi, Jae-Joon Han
  • Publication number: 20230100773
    Abstract: The substrate treating apparatus includes a liquid supply unit for supplying a treating liquid to a substrate supported by a support unit, the liquid supply unit includes a nozzle member for discharging the treating liquid; and a driving member for moving the nozzle member to a standby position and a process position, the nozzle member includes a body having a buffer space and a discharge port configured to discharge the treating liquid; and a rotation member for changing the body between a first state and a second state by a rotation, the first state is a state at which a treating liquid filled in the buffer space is maintained so the treating liquid does not flow to the discharge port, and the second state is a state at which the treating liquid filled in the buffer space is discharged to an outside of the body through the discharge port.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 30, 2023
    Applicant: SEMES CO., LTD.
    Inventors: Gi Hun CHOI, Young Joon HAN
  • Patent number: 11614424
    Abstract: A method of synthesizing an oligonucleotide using a nanofluidic device including a plurality of nanopore channels, a plurality of electrodes, and an electrolyte solution, includes coupling a primer to an inner wall of a nanopore channel of the plurality of nanopore channels, the primer having a protecting group. The method also includes applying a voltage to an electrode of the plurality of electrodes that corresponds to the nanopore channel to produce an acid from the electrolyte solution at the electrode. The electrode includes an anode and a cathode disposed at opposite sides of the nanopore channel. The method further includes the acid removing the protecting group from the primer. Moreover, the method includes coupling a nucleotide to the primer with the protecting group removed to form an intermediate product. In addition, the method includes repeating the steps on the intermediate product until the oligonucleotide is synthesized.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: March 28, 2023
    Assignee: PALOGEN, INC.
    Inventors: Bita Karimirad, Kyung Joon Han
  • Patent number: 11596947
    Abstract: An all-in-one self test kit includes: a test tool having a reagent container adapted to store a diagnosis reagent therein and a diagnosis kit with a casing constituted of a first body and a second body and a diagnosis strip disposed inside the casing and having a sucking part for sucking the diagnosis reagent and a diagnosis part reacting to the diagnosis reagent sucked to the sucking part; a sub-body having a container insertion portion for inserting the reagent container thereinto and a kit insertion portion for inserting the diagnosis kit thereinto; a main body for inserting the sub-body thereinto; and a cap fastened and unfastened with an entrance of the main body to open and close the main body.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: March 7, 2023
    Inventor: Kyung-Joon Han
  • Publication number: 20230036013
    Abstract: An all-in-one self test kit includes: a test tool having a reagent container adapted to store a diagnosis reagent therein and a diagnosis kit with a casing constituted of a first body and a second body and a diagnosis strip disposed inside the casing and having a sucking part for sucking the diagnosis reagent and a diagnosis part reacting to the diagnosis reagent sucked to the sucking part; a sub-body having a container insertion portion for inserting the reagent container thereinto and a kit insertion portion for inserting the diagnosis kit thereinto; a main body for inserting the sub-body thereinto; and a cap fastened and unfastened with an entrance of the main body to open and close the main body.
    Type: Application
    Filed: February 3, 2022
    Publication date: February 2, 2023
    Inventor: Kyung-Joon HAN
  • Publication number: 20230012958
    Abstract: A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (?m) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 ?m or less.
    Type: Application
    Filed: September 29, 2022
    Publication date: January 19, 2023
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Il Kwon Shim, Byung Joon Han
  • Publication number: 20230021306
    Abstract: A lightened neural network method and apparatus. The neural network apparatus includes a processor configured to generate a neural network with a plurality of layers including plural nodes by applying lightened weighted connections between neighboring nodes in neighboring layers of the neural network to interpret input data applied to the neural network, wherein lightened weighted connections of at least one of the plurality of layers includes weighted connections that have values equal to zero for respective non-zero values whose absolute values are less than an absolute value of a non-zero value. The lightened weighted connections also include weighted connections that have values whose absolute values are no greater than an absolute value of another non-zero value, the lightened weighted connections being lightened weighted connections of trained final weighted connections of a trained neural network whose absolute maximum values are greater than the absolute value of the other non-zero value.
    Type: Application
    Filed: January 12, 2022
    Publication date: January 19, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Changyong SON, Jinwoo SON, Byungin YOO, Chang Kyu CHOI, Jae-Joon HAN
  • Publication number: 20230015504
    Abstract: A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die.
    Type: Application
    Filed: September 26, 2022
    Publication date: January 19, 2023
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, Yaojian Lin, Pandi C. Marimuthu
  • Patent number: 11532177
    Abstract: A face verification method and apparatus is disclosed. The face verification method includes selecting a current verification mode, from among plural verification modes, to be implemented for the verifying of the face, determining one or more recognizers, from among plural recognizers, based on the selected current verification mode, extracting feature information from information of the face using at least one of the determined one or more recognizers, and indicating whether a verification is successful based on the extracted feature information.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: December 20, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changyong Son, Deoksang Kim, Minsu Ko, Jinwoo Son, Seungju Han, Chang Kyu Choi, Jae-Joon Han
  • Patent number: 11488933
    Abstract: A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (?m) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 ?m or less.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: November 1, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Il Kwon Shim, Byung Joon Han
  • Patent number: 11485569
    Abstract: One aspect of the present disclosure provides a wipe container allowing a cleaning wipe to be withdrawn without contact, the wipe container including a container main body configured to provide a space in which the cleaning wipe is stored, a container cover detachably coupled to an upper portion of the container main body to seal the container main body and control opening and closing of the container main body, a sub-cover provided in a portion of the container cover and whose opening and closing is controlled by pressure caused by an external force to seal the container main body, and withdrawal tongs inserted into the container main body due to having a portion coupled to the sub-cover and configured to be caught on the cleaning wipe accommodated in the container main body, wherein the withdrawal tongs include a coupling portion manufactured in a shape that corresponds to the sub-cover and detachably coupled to the sub-cover, a hook formed to protrude from a portion of a lower portion of the coupling porti
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: November 1, 2022
    Assignee: PaaNeeCo, Inc.
    Inventor: Steven Joon Han
  • Patent number: 11488932
    Abstract: A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: November 1, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, Yaojian Lin, Pandi C. Marimuthu
  • Publication number: 20220297923
    Abstract: One aspect of the present disclosure provides a wipe container allowing a cleaning wipe to be withdrawn without contact, the wipe container including a container main body configured to provide a space in which the cleaning wipe is stored, a container cover detachably coupled to an upper portion of the container main body to seal the container main body and control opening and closing of the container main body, a sub-cover provided in a portion of the container cover and whose opening and closing is controlled by pressure caused by an external force to seal the container main body, and withdrawal tongs inserted into the container main body due to having a portion coupled to the sub-cover and configured to be caught on the cleaning wipe accommodated in the container main body, wherein the withdrawal tongs include a coupling portion manufactured in a shape that corresponds to the sub-cover and detachably coupled to the sub-cover, a hook formed to protrude from a portion of a lower portion of the coupling porti
    Type: Application
    Filed: August 4, 2021
    Publication date: September 22, 2022
    Inventor: Steven Joon HAN