Abstract: The present invention relates to an output voltage stabilization circuit. Specifically, the present invention relates to an output voltage stabilization circuit of a display device driving circuit, which generates a reference current dependent on a high source voltage using a current source independent of a magnitude of the high source voltage, generates a reference current dependent on a low source voltage using a current source independent of a magnitude of the low source voltage, and then generates a control signal by comparing the magnitudes to each other, whereby the output voltage stabilization circuit may stabilize an output voltage regardless of an order in which the low source voltage and the high source voltage are turned off in a circuit using both the low source voltage and the high source voltage.

Abstract: Disclosed are a driving circuit of a display apparatus and a driving chip, which shuts off the output of image data, in a display apparatus in which a plurality of driving chips is connected to each other in a daisy chain method to correspond to a single display panel, when serial communication of the driving chips is not completed successfully, or when any one of the driving chips is not operated normally, thereby preventing an abnormal screen from being displayed.

Abstract: Provided is a driver IC chip of a liquid crystal display (LCD). The driver IC chip has a layout of power pads, which may uniformly apply an adhesive force on the entire adhesion surface of the driver IC chip, when the driver IC chip is mounted on a display panel according to a chip-on-glass (COG) technique.

Abstract: A method for routing gamma voltages in a flat panel display that includes a plurality of source driver integrated circuits (SDICs) each having a plurality of gamma buffers. The method includes forming routing lines to route a plurality of gamma voltages; connecting the routing lines to output terminals of the gamma buffers; applying the reset gamma voltage to the gamma buffer of selected SDIC after selecting the SDIC in which the gamma voltage is required to be reset in consideration of heating values of the SDICs, and changing connection between a routing line corresponding to the selected gamma buffer and a tap point of a resistor string of the SDIC such that the connection corresponds to the reset gamma voltage.

Abstract: A liquid crystal display driving circuit and method. A data register block of a controller applies in advance a polarity control signal to data before the data are stored in latches of a data driver, exchanges the data, and then stores the exchanged data in the latches. Thereby, it is possible to provide multiplexers, which are otherwise required for respective channels, to one controller and to decrease the size of a chip.

Abstract: Disclosed is a technique, in which when driving chips are used in which control units are respectively merged in driving devices, all modes of the other driving chips are simultaneously converted into a fail safe mode when one driving chip detects a non-signal state. A circuit for controlling a non-signal of a flat panel display device includes a plurality of driving chips. When detecting a non-signal state that the normal signal (LVDS) is not inputted from an outside, each of the plurality of driving chips simultaneously changes potentials of non-signal detection pads of its own driving chip and another driving chip so that all the driving chips are operated in the fail safe mode.

Abstract: An LCD driving circuit includes a first buffer configured to have a terminal for a first voltage, a terminal for a second voltage and a terminal for an intermediate voltage between the first voltage and the second voltage, and be driven in a range from the first voltage to the intermediate voltage; and a second buffer configured to have a terminal for the first voltage, a terminal for the second voltage and a terminal for the intermediate voltage, and be driven in a range from the intermediate voltage to the second voltage. The terminal for the intermediate voltage of the first buffer and the terminal for the intermediate voltage of the second buffer are connected with each other, and the first voltage is a highest voltage, the second voltage is a lowest voltage, and the intermediate voltage is in a range from the first voltage to the second voltage.

Abstract: Disclosed is a liquid crystal display panel driving circuit for driving a liquid crystal display panel with a resolution of N bits. N-bit digital data including upper X bits and lower Y bits is inputted. The liquid crystal display panel driving circuit includes a resistor string unit according to areas, a DAC converter switching unit according to areas, and an interpolation amplifier. The resistor string unit outputs analog reference voltages at different ratios according to three areas. The DAC converter switching unit receives the N-bit digital data, selects (Y+1) analog voltages from the analog reference voltages based on the upper X bits, outputs the (Y+1) analog voltages, and outputs the (Y+1) analog voltages of different combinations based on the lower Y bits. The interpolation amplifier receives the (Y+1) analog voltages and generates an interpolated output voltage by setting weights for the (Y+1) analog voltages by using multi-factors.

Abstract: Disclosed are a display driving circuit and a display device. The display driving circuit includes an output buffer unit that outputs a pair of pixel signals, an output switch unit that directly transfers the pair of pixel signals to a pair of output lines or transfers the pair of pixel signals to the pair of output lines such that the pair of pixel signals cross each other in correspondence with repetitive panel charging/discharging periods, and a charge sharing switch unit that controls charge sharing of the pair of output lines in correspondence with a charge sharing period between the panel charging/discharging periods, and provides a variable connection resistance value for the charge sharing. Consequently, power consumption and heat generation of the display driving circuit are reduced.

Abstract: Disclosed is a liquid crystal panel driving circuit of display stabilization, including: a plurality of output buffers buffering data voltage and supplying or cutting off the buffered data voltage to or from each of the plurality of data lines; an output MUX switch receiving outputs from two adjacent output buffers of the plurality of output buffers and transferring one of the two outputs to the plurality of data lines; a garbage switch connecting each of the plurality of data lines to a ground terminal; and a power on sensor or a power off sensor generating a power on or off reset signal in response to a turn on/off of a power supply voltage, wherein the output MUX switch is turned-off and the charge share switch and the garbage switch are turned-on, in response to the power on reset signal or the power off reset signal.

Abstract: Disclosed is a display driving circuit including an output buffer unit that is connected to a common voltage and first and second voltages and outputs a pair of pixel signals; an output switch that directly connects the pair of pixel signals to a pair of output lines or connects the pair of pixel signals to the pair of output lines such that they cross each other; and a pre-charging unit that charges the pair of output lines by using pre-charging voltages. Consequently, power consumption and heat generation of the display driving circuit are reduced.

Abstract: Provided is a technology for preventing noisy data from being displayed before valid data is inputted when power is turned on in a liquid crystal display.

Abstract: The present invention aims to provide a driving control circuit of a display device, which includes a plurality of data driving circuits each having a timing controller merged with a source driver. The data driving circuits are configured to synchronize data of the respective data driving circuits and compensate for a difference between a data enable signal and a gate output enable signal, when an abnormal display signal is received.

Abstract: The present invention relates to a display driving circuit and a display driving system, and more particularly, to a display driving circuit having a half-VDD power supply circuit built therein and a display driving system including the same, in which the display driving circuit is further provided with a half voltage VDD terminal in addition to the highest voltage VDD terminal and the lowest voltage VSS terminal, and the half voltage, which is between the highest voltage and the lowest voltage, is generated and supplied by the half voltage power supply from the inside of the display driving circuit, rather than being supplied from an external power supply.

Abstract: Embodiments of the present invention provide a method and apparatus for transmitting data between a timing controller and a source driver. In some embodiments, the method includes a bit error rate test (BERT) function for sensing an error rate in real time when data is transmitted and received between the timing controller and the source driver.

Abstract: Provided is a COG panel system capable of minimizing a block dim effect by considering a relationship among a plurality of chips. The COG panel system includes: an FPC which supplies at least two power supply voltages having a constant voltage level; a plurality of SDIs which are commonly supplied with a bypass power supply voltage from the FPC and generate respective parts of a plurality of consecutive LCD driving signals required for an arbitrary one line of an LCD; and at least one block dim correction resistance.

Abstract: The present invention aims to provide a driving control circuit of a display device that is capable of preventing an unnatural black screen. To this end, the driving control circuit is configured to include a plurality of TMICs, each of which is merged with a timing controller and a source driver, and the time controller is configured to adjust end locations of the horizontal blank intervals of data enable signals to match the end locations outputted from TMICs to an end location of a horizontal blank interval of a data enable signal outputted from another TMIC, and, when a gate output enable signal is supplied, perform adjustment so as to indicate a rising edge of the gate output enable signal before the data latch enable signal having the highest frequency is supplied.

Abstract: A circuit for measuring a capacitance value of a touch screen includes: a target capacitor unit having a target capacitor charged with a target charging voltage; a target voltage control unit to charge the target capacitor; a reference capacitor unit having a reference capacitor charged with a charging reference voltage; a reference voltage control unit to charge the reference capacitor; a comparator to compare the target charging voltage and the charging reference voltage and output a transition signal at a moment when the target charging voltage becomes higher than the charging reference voltage; and a controller to receive an output signal of the comparator and a clock signal and generate a digital output signal and a control signal, wherein a capacitance value of the target capacitor is measured using a time elapsed from a time when the target capacitor is initialized to a time when the transition signal is outputted.

Abstract: Provided is a driver IC chip of a liquid crystal display (LCD). The driver IC chip has a layout of power pads, which may uniformly apply an adhesive force on the entire adhesion surface of the driver IC chip, when the driver IC chip is mounted on a display panel according to a chip-on-glass (COG) technique.

Abstract: Provided is a method of driving a liquid crystal display apparatus, and more particularly, to a method of generating a frame start pulse signal for instructing driving of a specific function of a source driver in a source driver chip of a liquid crystal display apparatus. Accordingly, by generating a frame start pulse signal for instructing driving of a specific function of a source driver in a source driver chip unlike a conventional method where the frame start pulse signal is externally input, it is possible to reduce the number of input pins for inputting the frame start pulse signal and to remove an input line for inputting the frame start pulse signal in a process of mounting the source driver chip in a printed circuit board.