Abstract: An touch screen liquid crystal display device includes a panel driving circuit including a gate driving block, a data driving block, and a signal control block and a liquid crystal module that stores data in data pixels through a data pixel line, to which the data pixels are connected, in response to a data signal applied from the data driving block, and reads data through a read pixel line to which read pixels are connected. The read pixels are connected to the data pixels through a share line.

Abstract: Provided is a timing adjusting method for a touch screen liquid crystal display device. A liquid crystal module of the touch screen liquid crystal display device has a structure in which a data line connected to data pixels and a read line connected to read pixels are shared by a share line, and a display mode section for displaying data of the data pixels is performed separately from a read mode section for reading data of the read pixels.

Abstract: Provided is a method of driving a liquid crystal display apparatus, and more particularly, to a method of generating a frame start pulse signal for instructing driving of a specific function of a source driver in a source driver chip of a liquid crystal display apparatus. Accordingly, by generating a frame start pulse signal for instructing driving of a specific function of a source driver in a source driver chip unlike a conventional method where the frame start pulse signal is externally input, it is possible to reduce the number of input pins for inputting the frame start pulse signal and to remove an input line for inputting the frame start pulse signal in a process of mounting the source driver chip in a printed circuit board.

Abstract: Disclosed is a power supply line in which a voltage drop generated in a resistance component of a metal line which delivers a power voltage is minimized so that the level of the power supply voltage delivered to a semiconductor chip becomes constant in the entire area of the semiconductor chip. The semiconductor chip includes: at least two power supply pads to which a power voltage applied from an external unit of the semiconductor chip is supplied; power supply main metal lines connected to each of the power supply pads; power supply branch metal lines extended from each of the power supply main metal lines to deliver a power voltage to a circuit in the semiconductor chip; and at least an electrostatic discharge (ESD) improvement dummy pad, wherein the ESD improvement dummy pad is electrically connected to the corresponding power supply main metal line and the corresponding power supply branch metal line to minimize a voltage drop.

Abstract: Disclosed are an offset compensation gamma buffer and a gray scale voltage generation circuit using the same. The offset compensation gamma buffer includes: a buffer which outputs an input voltage input to a positive or negative input terminal as an output voltage; and a switching unit which selectively connects the input voltage and the output voltage of the buffer to the positive and negative input terminals in response to a control signal. The output voltage of the offset compensation gamma buffer is supplied to the input of a gray scale voltage generation circuit of a source driver for driving a liquid crystal panel. The offset of the offset compensation gamma buffer is compensated using an inversion timing of the control signal. The output voltage of the offset compensation gamma buffer is supplied as a reference voltage of the voltage divider unit for generating the gray scale voltages, and the offset of the gray scale voltages is also compensated.

Abstract: Provided is a pad layout structure of a semiconductor chip capable of preventing lead-broken problems when packaging the semiconductor chip with a high aspect ratio in a tape carrier package (TCP). In the pad layout structure of the semiconductor chip, a plurality pads are arranged along upper, lower, left and right sides of the semiconductor chip with a high aspect ratio, and a longitudinal width of pads arranged at the left and right sides and a transverse width of pads arranged at both edges of the upper and lower sides are greater than a transverse width of pads arranged at centers of the upper and lower sides.

Abstract: Provided are a method of arranging gamma buffers capable of decreasing a Kelvin of a source driver included in a flat panel display and minimizing a temperature deviation between source drivers, and the flat panel display applying the method. The method of arranging a plurality of gamma buffers which are arranged in one or more source drivers to output corresponding gamma voltages, includes a step of calculating power consumptions of the gamma buffers, wherein the method further comprises one or more steps of: changing tab points of the gamma buffers by using the calculated power consumptions of the gamma buffers; and changing positions of the gamma buffers by using the calculated power consumptions of the gamma buffers.

Abstract: A method of removing offsets between channels of a liquid crystal panel is provided. The method includes: alternately arranging first type output buffers and second type output buffers for driving the pixels in units of at least two rows of the pixels; and arranging the first type output buffers and the second type output buffers in units of at least two columns of the pixels so that the output buffers with types opposite to those of previous two columns are arranged. The second type output buffers are embodied by switching connections among the differential transistors and connections among the load transistors in the first type output buffers.

Abstract: Provided are a semiconductor integrated circuit having a heat release pattern in a chip so as to release heat generated inside the chip and a system board having a heat release unit used to release heat generated inside the semiconductor integrated circuit. The semiconductor integrated circuit includes: one or more output pads directly connected to an output terminal having a heat release pattern; a power supply pad supplying power; and one or more dummy pads connected to a metal line for supplying power or an internal output terminal of an internal function block, wherein the heat release pattern includes a plurality of unit contacts at the output terminal or a plurality of strip contacts having an area of about or larger than the sum of two or more of the unit contacts.

Abstract: An input buffer circuit compensates for a data hold time and reduces an operational current by implementing a delay operation with transistors having a long channel when the input buffer circuit is driven by a high external voltage. The input buffer circuit includes a delay unit to delay an input signal, the delay unit being powered by an external power voltage and having an associated variable delay which is varied according to a detection signal and the external power voltage, the detection signal indicating whether the external power voltage is high or low.

Abstract: A data input buffer circuit is disclosed.

Abstract: A semiconductor memory device according to the present invention includes a write pulse width timing compensating part that controls a write pulse width timing. The semiconductor memory controls the point of disabling a write control drive signal by directly producing a write enable signal or delaying the write enable signal based on a level of a power supply voltage to compensate the write pulse width timing. The write pulse width timing compensating part receives the poser supply level and the write enable signal and outputs a compensated write control drive signal. A generating part receives the write control drive signal from the write pulse width timing compensating part, a selection signal, and a decoder signal and generates a control signal. A data input part writes input data to a selected cell upon application of data and the control signal from the generating part.

Abstract: A memory chip having a multiple input/output system enables a memory to have a .times.n, .times.2n or .times.4n I/O system through a simple fuse mask process by using a single memory chip and reduces the consumption of a cell current while having a memory capacity which is the same as in the .times.n or .times.2n I/O system of the conventional art.

Abstract: A write control driver circuit writes a data in a high-speed semiconductor chip by obtaining an earlier enabling time of a write control signal. The circuit includes a first logic circuit unit that outputs a first pulse signal of an address transition detection signal based on an input write enable signal, a second pulse signal of an address transition detection signal generated after the first pulse signal, and a delay control signal in which the first pulse signal is removed when the first and second pulse signals are inputted thereto. A second logic circuit unit that receives the delay control signal and a coding signal and output a write control signal.

Abstract: A write control driver circuit stores a data in a high speed chip by causing an enabling timing of a write control signal to become faster. The circuit includes a first logic circuit for receiving a peri-top address transition detection signal and a peri-bottom address transition detection signal, and a second logic circuit for receiving a combined address transition detection signal, a coding signal and a write driver signal, each having a predetermined width. The combined address transition detection signal is generated based on a delay unit having a prescribed pulse width. The second logic circuit outputs a write control signal that is not controlled by the peri-top address transition detection signal and the peri-bottom address transition detection signal.