Patents by Inventor Joung-Wei Liou

Joung-Wei Liou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10181443
    Abstract: Among other things, one or more support structures and techniques for forming such support structures within semiconductor devices are provided. The support structure comprises an oxide infused silicon layer that is formed within a trench of a dielectric layer on a substrate of a semiconductor device. The oxide infused silicon layer results from a silicon layer that is exposed to oxide during an ultraviolet (UV) curing process. The oxide infused silicon layer is configured to support a barrier layer against a conductive structure formed on the barrier layer within the trench. In this way, the support structure provides pressure against the barrier layer so that the barrier layer substantially maintains contact with the conductive structure, to promote improved performance and reliability of the conductive structure.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: January 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Joung-Wei Liou, Keng-Chu Lin
  • Patent number: 10134632
    Abstract: A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Joung-Wei Liou, Hui-Chun Yang, Yu-Yun Peng, Keng-Chu Lin
  • Publication number: 20180308665
    Abstract: A wafer process chamber includes a wafer support in the wafer process chamber, the wafer support configured to support a wafer. The process chamber includes a gas diffuser unit within the wafer process chamber. The gas diffuser unit includes at least one controllable diffuser configured to generate one or more controllable forces acting in various directions on a gaseous material in a flow of the gaseous material introduced into the process chamber, to spread the gaseous material inside the process chamber. The gas diffuser unit includes a power source coupled to the at least one controllable diffuser, the power source configured to supply power to the at least one controllable diffuser to generate the one or more controllable forces. The gas diffuser unit includes a controller coupled to the power source, the controller configured to control the power supplied by the power source to the at least one controllable diffuser.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 25, 2018
    Inventors: Chien Kuo HUANG, Shih-Wen HUANG, Joung-Wei LIOU, Chia-I SHEN, Fei-Fan CHEN
  • Patent number: 10008367
    Abstract: A gas diffuser unit for a process chamber includes at least one controllable diffuser, a power source, and a controller. The at least one controllable diffuser is configured to generate controllable forces acting in various directions on a gaseous material in a flow of the gaseous material introduced into the process chamber, to spread the gaseous material inside the process chamber. The power source is coupled to the at least one controllable diffuser, and configured to supply power to the at least one controllable diffuser to generate the controllable forces. The controller is coupled to the power source and configured to control the power supplied by the power source to the at least one controllable diffuser.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: June 26, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien Kuo Huang, Shih-Wen Huang, Joung-Wei Liou, Chia-I Shen, Fei-Fan Chen
  • Patent number: 9941214
    Abstract: Semiconductor devices, methods of manufacture thereof, and IMD structures are disclosed. In some embodiments, a semiconductor device includes an adhesion layer disposed over a workpiece. The adhesion layer has a dielectric constant of about 4.0 or less and includes a substantially homogeneous material. An insulating material layer is disposed over the adhesion layer. The insulating material layer has a dielectric constant of about 2.6 or less. The adhesion layer and the insulating material layer comprise an IMD structure.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: April 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Yun Peng, Keng-Chu Lin, Joung-Wei Liou, Kuang-Yuan Hsu
  • Patent number: 9870944
    Abstract: A method of fabricating an interconnect structure on a wafer and an interconnect structure are provided. A dielectric layer is provided on the wafer, with the dielectric layer having a recess therein. A silicon (Si) layer is deposited in the recess. An interconnect is formed by providing a barrier layer and a conductive layer in the recess over the Si layer. The Si layer has a density that prevents or substantially prevents the barrier layer from moving away from the conductive layer and towards the dielectric layer during subsequent processing of the interconnect structure.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Joung-Wei Liou, Keng-Chu Lin
  • Patent number: 9812390
    Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming conductive features thereof are disclosed. A semiconductor device includes an insulating material layer disposed over a workpiece. The insulating material layer includes a silicon-containing material comprising about 13% or greater of carbon (C). A conductive feature is disposed within the insulating material layer. The conductive feature includes a capping layer disposed on a top surface thereof.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: November 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Chun Yang, Mei-Ling Chen, Keng-Chu Lin, Joung-Wei Liou
  • Patent number: 9748175
    Abstract: A method for manufacturing a semiconductor structure is provided. The method for manufacturing a semiconductor structure includes forming an organosilicon layer over a substrate and etching the organosilicon layer to have a trench. The method for manufacturing a semiconductor structure further includes forming a conductive structure in the trench. In addition, the organosilicon layer is made of a material including Si—C bonding and Si—O bonding, and a ratio of an amount of the Si—C bonding to an amount of the Si—O bonding is greater than about 0.2.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Jung Liu, Huan-Wei Wu, Chester Tang, Joung-Wei Liou
  • Patent number: 9748134
    Abstract: A method of making a semiconductor device including forming a first adhesion layer over a substrate. The method further includes forming a second adhesion layer over the first adhesion layer, where the second adhesion layer is formed using an inert gas with a first flow rate under a first RF power. Additionally, the method includes forming a low-k dielectric layer over the second adhesion layer, where the low-k dielectric layer is formed using the inert gas with a second flow rate under a second RF power under at least one of the following two conditions: 1) the second flow rate is different from the first flow rate; or 2) the second RF power is different from the first RF power. Furthermore, the method includes forming an opening in the dielectric layer, the second adhesion layer, and the first adhesion layer. Additionally, the method includes forming a conductor in the opening.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Cheng Shih, Yu-Yun Peng, Chia Cheng Chou, Joung-Wei Liou
  • Publication number: 20170148676
    Abstract: A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5.
    Type: Application
    Filed: February 6, 2017
    Publication date: May 25, 2017
    Inventors: Joung-Wei Liou, Hui-Chun Yang, Yu-Yun Peng, Keng-Chu Lin
  • Patent number: 9564383
    Abstract: A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: February 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Joung-Wei Liou, Hui-Chun Yang, Yu-Yun Peng, Keng-Chu Lin
  • Publication number: 20160259246
    Abstract: A system and method for depositing a photoresist and utilizing the photoresist are provided. In an embodiment a deposition chamber is utilized along with a first precursor material comprising carbon-carbon double bonds and a second precursor material comprising repeating units to deposit the photoresist onto a substrate. The first precursor material is turned into a plasma in a remote plasma chamber prior to being introduced into the deposition chamber. The resulting photoresist comprises a carbon backbone with carbon-carbon double bonds.
    Type: Application
    Filed: May 16, 2016
    Publication date: September 8, 2016
    Inventors: Keng-Chu Lin, Joung-Wei Liou, Cheng-Han Wu, Ya Hui Chang
  • Publication number: 20160260667
    Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming conductive features thereof are disclosed. A semiconductor device includes an insulating material layer disposed over a workpiece. The insulating material layer includes a silicon-containing material comprising about 13% or greater of carbon (C). A conductive feature is disposed within the insulating material layer. The conductive feature includes a capping layer disposed on a top surface thereof.
    Type: Application
    Filed: May 17, 2016
    Publication date: September 8, 2016
    Inventors: Hui-Chun Yang, Mei-Ling Chen, Keng-Chu Lin, Joung-Wei Liou
  • Publication number: 20160197043
    Abstract: Among other things, one or more support structures and techniques for forming such support structures within semiconductor devices are provided. The support structure comprises an oxide infused silicon layer that is formed within a trench of a dielectric layer on a substrate of a semiconductor device. The oxide infused silicon layer results from a silicon layer that is exposed to oxide during an ultraviolet (UV) curing process. The oxide infused silicon layer is configured to support a barrier layer against a conductive structure formed on the barrier layer within the trench. In this way, the support structure provides pressure against the barrier layer so that the barrier layer substantially maintains contact with the conductive structure, to promote improved performance and reliability of the conductive structure.
    Type: Application
    Filed: January 5, 2015
    Publication date: July 7, 2016
    Inventors: Joung-Wei Liou, Keng-Chu Lin
  • Patent number: 9379061
    Abstract: Some embodiments of the present disclosure relate to an integrated circuit device. The integrated circuit device includes a semiconductor substrate, and an inter-level dielectric layer arranged over the semiconductor substrate. An etch-stop layer is arranged over the inter-level dielectric layer. The etch-stop layer comprises silicon oxide, silicon nitride, or silicon oxynitride, and has a density greater than or equal to 2.15 g/cm3.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Joung-Wei Liou, Han-Ti Hsiaw, Keng-Chu Lin
  • Patent number: 9373581
    Abstract: Interconnect structures and methods for forming the same are described. A method for forming an interconnect structure may include: forming a low-k dielectric layer over a substrate; forming an opening in the low-k dielectric layer; forming a conductor in the opening; forming a capping layer over the conductor; and forming an etch stop layer over the capping layer and the low-k dielectric layer, wherein the etch stop layer has a dielectric constant ranging from about 5.7 to about 6.8.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: June 21, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Cheng Shih, Joung-Wei Liou, Chih-Hung Sun, Chia-Cheng Chou, Kuang-Yuan Hsu
  • Publication number: 20160155663
    Abstract: A method of making a semiconductor device including forming a first adhesion layer over a substrate. The method further includes forming a second adhesion layer over the first adhesion layer, where the second adhesion layer is formed using an inert gas with a first flow rate under a first RF power. Additionally, the method includes forming a low-k dielectric layer over the second adhesion layer, where the low-k dielectric layer is formed using the inert gas with a second flow rate under a second RF power under at least one of the following two conditions: 1) the second flow rate is different from the first flow rate; or 2) the second RF power is different from the first RF power. Furthermore, the method includes forming an opening in the dielectric layer, the second adhesion layer, and the first adhesion layer. Additionally, the method includes forming a conductor in the opening.
    Type: Application
    Filed: February 8, 2016
    Publication date: June 2, 2016
    Inventors: Po-Cheng Shih, Yu-Yun Peng, Chia Cheng Chou, Joung-Wei Liou
  • Patent number: 9349689
    Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming conductive features thereof are disclosed. A semiconductor device includes an insulating material layer disposed over a workpiece. The insulating material layer includes a silicon-containing material comprising about 13% or greater of carbon (C). A conductive feature is disposed within the insulating material layer. The conductive feature includes a capping layer disposed on a top surface thereof.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: May 24, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Chun Yang, Mei-Ling Chen, Keng-Chu Lin, Joung-Wei Liou
  • Patent number: 9341945
    Abstract: A system and method for depositing a photoresist and utilizing the photoresist are provided. In an embodiment a deposition chamber is utilized along with a first precursor material comprising carbon-carbon double bonds and a second precursor material comprising repeating units to deposit the photoresist onto a substrate. The first precursor material is turned into a plasma in a remote plasma chamber prior to being introduced into the deposition chamber. The resulting photoresist comprises a carbon backbone with carbon-carbon double bonds.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: May 17, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Chu Lin, Joung-Wei Liou, Cheng-Han Wu, Ya Hui Chang
  • Patent number: 9269614
    Abstract: A method of forming a semiconductor device comprises forming a first etch stop layer over a substrate. The method also comprises forming a low-k dielectric layer comprising carbon over the first etch stop layer. The method further comprises forming an opening in the low-k dielectric layer. The method additionally comprises filling the opening with a conductive layer. The method also comprises performing a remote plasma treatment on the low-k dielectric layer and the conductive layer. The method further comprises forming a second etch stop layer over the treated conductive layer and the treated low-k dielectric layer.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: February 23, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Cheng Shih, Hui-Chun Yang, Chih-Hung Sun, Joung-Wei Liou