Abstract: The present disclosure relates to a contact point monitoring device for a vacuum circuit breaker, and a correction method performed through same, wherein deviations due to temperature in a sensor for monitoring the amount of wear at a contact point may be compensated for. According to the present disclosure, the amount of wear at the contact point may be accurately detected by correcting a characteristic value of a photosensor according to operation temperature, by taking into consideration the temperature characteristics of the photosensor.

Abstract: Disclosed are a memory system, a memory controller, and a method of operating the memory system. The memory system may configure a plurality of map cache pools for caching map data of different types, respectively, within a map cache in which the map data is cached, configure a timer in a first map cache pool among the plurality of map cache pools, and write map data cached in the first map cache pool in the memory device based on the timer.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may store target data to be programmed in a memory device in a first memory, selectively store the target data in a second memory, program the target data stored in the first memory into the memory device, and reprogram the target data stored in the first memory or the second memory into the memory device when the programming of the target data stored in the first memory into the memory device fails. The buffer circuit may input the target data input from the memory controller into the second memory or discard the target data.

Abstract: A memory system includes: a memory device including a plurality of memory dies including the plurality of planes; and a controller configured to store data in a plurality of stripes each including physical pages of different planes and a plurality of unit regions, the controller comprising: a processor configured to queue write commands in a write queue, and select, among the plurality of stripes, a stripe in which data chunks corresponding to the write commands are to be stored; and a striping engine configured to receive queued orders of the write commands, and output, by referring to a lookup table, addresses of unit regions, in which the data chunks are to be arranged, to the processor, wherein the processor in configured to control the memory device to store the data chunks in the unit regions corresponding to the outputted addresses of the selected stripe.

Abstract: A controller for controlling a memory device is provided to include: a request receiver configured to receive a request including a logical address from a host; a dependency checker configured to acquire the request from the request receiver and check a dependency of the request; a map manager configured to generate a command including a physical address mapped to the logical address of the request in response to a result of checking that the request has no dependency on the prior incomplete request; and a command submitter configured to provide the memory device with the command generated by the map manager, wherein the request receiver, the dependency checker, the map manager and the command submitter are structured to configure a data pipeline such that operations of the request receiver, the dependency checker, the map manager, and the command submitter deliver are performed in series.

Abstract: A muffler having a movable baffle may include a housing where an input pipe into which exhaust gas is flowed from an engine and an output pipe through which the exhaust gas is expelled to atmosphere are disposed, a baffle which is configured to be slidable along the longitudinal direction of the housing and divides the space of the housing, baffle moving means for moving the baffle to an arbitrary position within a predetermined range along the longitudinal direction of the housing, and a controller which data for determining whether to move the baffle or not is input thereto when the engine is driven, determines whether to move the baffle or not by use of the input data and controls the baffle moving means when the baffle is determined to be moved.

Abstract: A controller that controls a memory device including a plurality of pages each corresponding to a physical address, the controller may include: a memory suitable for storing a plurality of logical-to-physical (L2P) chunks each indicating mapping between one or more logical addresses and one or more physical addresses and an original valid page bitmap (VPB) indicating whether each of the plurality of pages is a valid page that stores valid data; and a processor suitable for generating a reconstructed VPB based on normal L2P chunks when an corrupted L2P chunk is detected, detecting pages having different states in the original VPB and the reconstructed VPB, obtaining logical addresses mapped to physical addresses of the detected pages, respectively, and recovering the corrupted L2P chunk based on the physical addresses of the detected pages and the obtained logical addresses.

Abstract: A memory system includes: a controller including first and second cores; a plurality of channels connected to the controller; a plurality of first memory devices each including first memory blocks allocated to the first core, each of the plurality of channels being coupled to at least one first memory device; and a plurality of second memory devices each including second memory blocks allocated to the second core, each of the plurality of channels being coupled to at least one second memory device, wherein the controller further includes: a global wear leveling manager configured to perform a global wear leveling operation by swapping a first memory block and a second memory block, which are connected to the same channel among the first memory blocks and the second memory blocks, between the first and second cores on the basis of wear levels of the first memory blocks and the second memory blocks.

Abstract: The present technology relates to an electronic device. According to the present technology, a storage device that manages map data using a volatile memory device having a limited capacity may include a nonvolatile memory device and a memory controller which includes a map chunk buffer, a map chunk status table, a journal buffer, and a meta slice buffer.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may store target data to be programmed in a memory device in a first memory, selectively store the target data in a second memory, program the target data stored in the first memory into the memory device, and reprogram the target data stored in the first memory or the second memory into the memory device when the programming of the target data stored in the first memory into the memory device fails. The buffer circuit may input the target data input from the memory controller into the second memory or discard the target data.

Abstract: Techniques are provided herein for creating well-balanced computer-based reasoning systems and using those to control systems. The techniques include receiving a request to determine whether to use one or more particular data elements, features, cases, etc. in a computer-based reasoning model (e.g., as data elements, cases or features are being added, or as part of pruning existing features or cases). Conviction measures are determined and inclusivity conditions are tested. The result of comparing the conviction measure can be used to determine whether to include or exclude the feature, case, etc. in the model and/or whether there are anomalies in the model. A controllable system may then be controlled using the computer-based reasoning model.

Abstract: Disclosed are a memory system, a memory controller, and a method of operating the memory system. The memory system may configure a plurality of map cache pools for caching map data of different types, respectively, within a map cache in which the map data is cached, configure a timer in a first map cache pool among the plurality of map cache pools, and write map data cached in the first map cache pool in the memory device based on the timer.

Abstract: A memory system comprising: a controller generates meta data in accordance with normal data being stored in a non-volatile memory device, and a buffer memory stores multiple meta slices configuring the meta data, the controller classifies an updated slice of the multiple meta slices as a first dirty slice, classifies a flushed slice of the first dirty slices as a second dirty slice, classifies a flushed slice of the second dirty slices as the meta slice and classifies an updated slice of the second dirty slices as a third dirty slice, classifies a flushed slice of the third dirty slices as the second dirty slice, and permits an update of each of the first to third dirty slices in a section in which a flush operation for each of the first to third dirty slices is performed.

Abstract: The present invention relates to a method for drying an electrode plate capable of solving an electrode plate overdrying problem and a drying uniformity deterioration problem due to a pressure change by including: a supply air volume setting step of setting an initial supply air volume introduced into a drier to a target air volume or less; an exhaust air volume setting step of setting an initial exhaust air volume to a numerical value corresponding to the initial supply air volume set in the supply air volume setting step; and an air volume adjusting step of increasing a supply air volume and an exhaust air volume from the initial air volumes set in the supply air volume setting step and the exhaust air volume setting step to designated target air volumes for a predetermined time, and a system for drying an electrode plate capable of effectively implementing the same.

Abstract: A diffractive optical element including a diffraction layer including a plurality of optical axes along an in-plane direction, wherein the diffraction layer includes an anisotropic material that satisfies one of Relationship Equations 1A to 3A ?n1(450 nm)<?n1(550 nm)??n1(650 nm)??Relationship Equation 1A ?n1(450 nm)??n1(550 nm)<?n1(650 nm)??Relationship Equation 2A ?n1(450 nm)=?n1(550 nm)=?n1(650 nm)??Relationship Equation 3A wherein, in Relationship Equations 1A to 3A, ?n1 (450 nm) is a birefringence of the anisotropic material at a wavelength of 450 nanometers, ?n1 (550 nm) is a birefringence of the anisotropic material at a wavelength of 550 nanometers, and ?n1 (650 nm) is a birefringence of the anisotropic material at a wavelength of 650 nanometers.

Abstract: The memory controller controls at least one memory device including a plurality of stream storage areas. The memory controller comprises a buffer, a write history manager, a write controller, and a garbage collection controller. The buffer stores write data. The write history manager stores write count values for each of the plurality of stream storage areas and generates write history information indicating a write operation frequency for each of the plurality of stream storage areas based on the write count values. The write controller controls the at least one memory device to store the write data provided from the buffer. The garbage collection controller controls the at least one memory device to perform a garbage collection operation on a target stream storage area selected from among the plurality of stream storage areas based on the write history information.

Abstract: A controller that controls a memory device including a plurality of pages each corresponding to a physical address, the controller may include: a memory suitable for storing a plurality of logical-to-physical (L2P) chunks each indicating mapping between one or more logical addresses and one or more physical addresses and an original valid page bitmap (VPB) indicating whether each of the plurality of pages is a valid page that stores valid data; and a processor suitable for generating a reconstructed VPB based on normal L2P chunks when an corrupted L2P chunk is detected, detecting pages having different states in the original VPB and the reconstructed VPB, obtaining logical addresses mapped to physical addresses of the detected pages, respectively, and recovering the corrupted L2P chunk based on the physical addresses of the detected pages and the obtained logical addresses.

Abstract: An electronic device includes a memory controller having an improved operation speed. The memory controller includes a processor configured to generate commands for accessing data stored in a main memory, a scheduling circuit configured to store the commands and output the commands according to a preset criterion, and a filtering circuit configured to store information on an address of the main memory corresponding to a write command among the commands, provide a pre-completion response for the write command to the scheduling circuit upon receiving the write command, and provide the write command to the main memory.

Abstract: Techniques are provided herein for creating well-balanced computer-based reasoning systems and using those to control systems. The techniques include receiving a request to determine whether to use one or more particular data elements, features, cases, etc. in a computer-based reasoning model (e.g., as data elements, cases or features are being added, or as part of pruning existing features or cases). Conviction measures are determined and inclusivity conditions are tested. The result of comparing the conviction measure can be used to determine whether to include or exclude the feature, case, etc. in the model and/or whether there are anomalies in the model. A controllable system may then be controlled using the computer-based reasoning model.

Abstract: The memory controller controls at least one memory device including a plurality of stream storage areas. The memory controller comprises a buffer, a write history manager, a write controller, and a garbage collection controller. The buffer stores write data. The write history manager stores write count values for each of the plurality of stream storage areas and generates write history information indicating a write operation frequency for each of the plurality of stream storage areas based on the write count values. The write controller controls the at least one memory device to store the write data provided from the buffer. The garbage collection controller controls the at least one memory device to perform a garbage collection operation on a target stream storage area selected from among the plurality of stream storage areas based on the write history information.