Abstract: The present disclosure generally relates to a translucid access method and apparatus to a host allowing access to data contained within the host.

Abstract: A storage system and method for adaptive scheduling of background operations are provided. In one embodiment, after a storage system completes a host operation in the memory, the storage system remains in a high power mode for a period of time, after which the storage system enters a low-power mode. The storage system estimates whether there will be enough time to perform a background operation in the memory during the period of time without the background operation being interrupted by another host operation. In response to estimating that there will be enough time to perform the background operation in the memory without the background operation being interrupted by another host operation, the storage system performs the background operation in the memory.

Abstract: Methods, apparatus and systems for data storage devices that include non-volatile memory (NVM) are described. One such apparatus includes a non-volatile memory, a data storage device controller configured to receive a command from a host device, and wherein the data storage device controller comprises a file system analyzer comprising a determination circuit configured to determine based on the command from the host device whether a logical block address (LBA) referenced in the command is part of a known file extent, and a selection circuit configured to select a flash translation layer (FTL) workflow for the file extent in response to the determination that the LBA referenced in the command is part of the known file extent.

Abstract: The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.

Abstract: The present disclosure generally relates to reducing boot latency of memory devices in a dual boot system. The boot code is loaded to the data storage device controller in a flexible manner by being able to receive chunks of the boot code from two separate locations, the host memory buffer (HMB) and the memory device, which may be a NAND device. Part of the boot code may be received from the HMB and another part of the boot code may be received from the memory device. If either the HMB or the memory device can deliver the chunks faster than the other, then the controller can receive the chunks from the faster location and periodically confirm the speed of delivery to ensure the boot code latency is optimized.

Abstract: Systems and methods for compacting and anonymizing telemetry data in a storage system. A controller of a storage device may generate telemetry data based on collected features indicative of the performance of the storage device. The controller may store the telemetry data in the telemetry memory of the storage device. The controller may then transform the telemetry data into transformed telemetry data based on a dimension reduction algorithm, and transmit the transformed telemetry data to the host device.

Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit. The capacity of the media unit is divided into a plurality of zones. The controller is configured to make informed use of errors by update zone metadata to indicate one or more first logical block addresses were skipped and to indicate the next valid logical block address is available to store data. The controller is further configured to update zone metadata to recommend to the host device to reset one or more full zones, to recommend to the host device to transition one or more open zones to a full state, to alert the host device that one or more open zones have been transitioned to the full state, and to notify the host device of the writeable zone capacity of each of the plurality of zones.

Abstract: The present disclosure generally relates to systems and methods by which a data storage device may receive data about the host system in which it is installed, and the customer associated with that system. Based upon this received data, the data storage device may modify its native operating parameters and custom functions to enable more optimal operation with the host system.

Abstract: An apparatus, system, and method for detecting compromised firmware in a non-volatile storage device. A control bus of a non-volatile storage device is monitored. The non-volatile storage device includes a processor and electronic components coupled to the control bus. Signal traffic on the control bus is analyzed for events and/or triggers related to storage operations initiated on the control bus by the processor. Storage operations include one or more commands directed to at least one of the electronic components. If the latency for the storage operation satisfies an alert threshold a host is notified of compromised firmware.

Abstract: The present disclosure generally relates to a flexible or soft architecture solution of a host-data storage device system. The host is permitted different, intermediate levels of responsibility to the memory management. The different levels of host involvement in the memory management of the memory device are anywhere between an existing zone namespace (ZNS) solution and an open channel solution. The data storage device offers a selection of specific memory management options to the host device. The host device then selects the level of memory management desired and configures the data storage device to meet the memory management selection. In so doing, the host device controls the trade-off between host device overhead of memory management and host device flexibility.

Abstract: A storage system and method for predictive block allocation for efficient garbage collection are provided. One method involves determining whether a memory in a storage system is being used in a first usage scenario or a second usage scenario; in response to determining that the memory is being used in the first usage scenario, using a first block allocation method; and in response to determining that the memory is being used in the second usage scenario, using a second block allocation method, wherein the first block allocation method allocates blocks that are closer to needing garbage collection than the second block allocation method.

Abstract: A storage system and method for stream management in a multi-host virtualized storage system are provided. In one embodiment, a method for stream management is provided that is performed in a storage system in communication with a host comprising a plurality of virtual hosts. The method comprises: receiving, from the host, identification of each virtual host of the plurality of virtual hosts; analyzing usage history of each virtual host of the plurality of virtual hosts; and assigning streams to a subset of the plurality of virtual hosts based on the usage history, wherein a maximum number of streams assignable by the storage system is less than a total number of virtual hosts in the plurality of virtual hosts. Other embodiments are provided.

Abstract: The present disclosure, in various aspects, describes technologies and techniques for a controller of a data storage device to mitigate temperature increases in the data storage device. In one example, the controller receives a command for a memory operation, analyzes the command to determine whether execution of the command with thermal throttling would have a negative impact on a user experience, and activates, if performing the thermal throttling would have the negative impact on the user experience, one or more thermoelectric cooler (TEC) devices while refraining from performing the thermal throttling. In another example, the controller monitors a temperature of one or more regions of the data storage device, determines whether the temperature exceeds a threshold temperature, activates one or more TEC devices to mitigate the temperature when the temperature exceeds the threshold temperature, and deactivates any activated TEC devices when the temperature no longer exceeds the threshold temperature.

Abstract: The disclosure relates in some aspects to a controller of a data storage device, such as the controller of a solid state device (SSD) having non-volatile memory (NVM). In some aspects, the controller operates to prevent or reduce page faults in the host device. In one example, an outer mapping table of a set of page tables of a host device stores pointers to an inner mapping table in the SSD controller. The pointers are provided within memory access requests sent from the host to the SSD. The inner table maps the pointers to physical addresses in the SSD. The SSD detects page faults by identifying pointers that do not have corresponding entries in the inner table. The SSD allocates physical addresses to accommodate such access requests, then executes the requests on behalf of the host device. In this manner, the page fault is transparent to the host.

Abstract: The present disclosure generally relates to a flexible or soft architecture solution of a host-data storage device system. The host is permitted different, intermediate levels of responsibility to the memory management. The different levels of host involvement in the memory management of the memory device are anywhere between an existing zone namespace (ZNS) solution and an open channel solution. The data storage device offers a selection of specific memory management options to the host device. The host device then selects the level of memory management desired and configures the data storage device to meet the memory management selection. In so doing, the host device controls the trade-off between host device overhead of memory management and host device flexibility.

Abstract: The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.

Abstract: Apparatus and methods for protecting in-flight data during a fundamental reset of a SSD by a connected host are presented. In embodiments, a controller for the SSD includes an input interface configured to receive commands from the host over a link, and processing circuitry coupled to the input interface. The processing circuitry is configured to, in response to receiving a reset command from the host, reset the link and an address space of the SSD, complete a flush of in-flight data from temporary buffers to non-volatile storage of the SSD, and, during an initialization sequence performed by the host, perform an internal reset. In embodiments, in response to the SSD performing the internal reset, the host's state of the SSD is reset, and the host is caused to re-initialize the link and configure the address space of the SSD.

Abstract: The present disclosure generally relates to scheduling zone-append commands for a zoned namespace (ZNS). Rather than taking zone-append commands in order or randomly, the zone-append commands can be scheduled in the most efficient manner consistent with the open zones of the ZNS. A zone priority is determined based upon the length of time that a zone has been open together with the zone status. Generally, the older the zone and/or the more full that a zone is increases the priority. Once the zone priority is established, the zone-append commands are scheduled to ensure the zone-append commands for the high priority zones are processed first so that the open zone can be filled prior to closing.

Abstract: A storage device includes a controller that can dynamically adjust the zone active limit (ZAL) for a zoned namespace (ZNS). Rather than assuming a worst-case scenario for the ZNS, the ZAL can be dynamically adjusted, even after providing the ZAL to a host device. In so doing, device behavior changes due to factors such as temperature, failed or flipped bit count, and device cycling can be considered as impacting the ZAL. The ZAL can then be adjusted over time, and the new ZAL can be communicated to the host device. As such, rather than a fixed, worst-case ZAL, the host device will receive updated ZAL values over time as the device performs.

Abstract: The present disclosure generally relates to power management for an external storage device. The external storage device includes a power allocation unit coupled to an array of memory devices. A single bridge is present to provide a connection to a host device. The memory devices have operational power states that utilize a first amount of power and non-operational power states that utilize a second amount of power that is less than the first amount of power. The power allocation unit changes the power state of the individual memory devices between operational and non-operational based upon need, but also ensures that the external storage device does not exceed the total power allocation. Thus, the power allocation unit may change a power state of one memory device from operational to non-operational in order to change the power state of another memory device from non-operational to operational.