Abstract: A storage device includes a controller that can dynamically adjust the zone active limit (ZAL) for a zoned namespace (ZNS). Rather than assuming a worst-case scenario for the ZNS, the ZAL can be dynamically adjusted, even after providing the ZAL to a host device. In so doing, device behavior changes due to factors such as temperature, failed or flipped bit count, and device cycling can be considered as impacting the ZAL. The ZAL can then be adjusted over time, and the new ZAL can be communicated to the host device. As such, rather than a fixed, worst-case ZAL, the host device will receive updated ZAL values over time as the device performs.

Abstract: The present disclosure generally relates to power management for an external storage device. The external storage device includes a power allocation unit coupled to an array of memory devices. A single bridge is present to provide a connection to a host device. The memory devices have operational power states that utilize a first amount of power and non-operational power states that utilize a second amount of power that is less than the first amount of power. The power allocation unit changes the power state of the individual memory devices between operational and non-operational based upon need, but also ensures that the external storage device does not exceed the total power allocation. Thus, the power allocation unit may change a power state of one memory device from operational to non-operational in order to change the power state of another memory device from non-operational to operational.

Abstract: A storage system and method for improved playback analysis are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to identify a plurality of frames in video data stored in the memory that differ from surrounding frames by more than a threshold amount; receive a request from a host for quick playback of the video data; and send the plurality of frames to the host. Other embodiments are provided.

Abstract: The present disclosure generally relates to a storage snapshot management system. When updated data is written to the memory device, rather than rewriting all of the data, only the updated data is written to a new namespace. A snapshot of the new namespace indicates which LBAs in the new namespace contain data. New namespaces are added each time data is updated. When the updated data is to be read, the data storage device reads the updated LBA from the new namespace, and also gathers the non-updated data from the previous namespace. Eventually, the number of namespaces for the data reaches a threshold, and thus some namespaces need to be evicted. To evict a namespace, the updated data in the namespace is moved to a different namespace, or the non-updated data is moved to a namespace that contains updated data. In either case, the now unused namespaces are evicted.

Abstract: A storage system and method for reducing read-retry duration are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to: receive a command from a host; and in response to an interruption in processing of the command: select a time for the host to retry the command, wherein the time is selected based on an expected host response time; and communicate the selected time to the host. Other embodiments are provided.

Abstract: An apparatus includes a plurality of non-volatile memory cells and control circuitry connected to the plurality of non-volatile memory cells. The control circuitry is configured to receive write commands from a host and identify write commands associated with temporary data. In a recovery operation, control data associated with the temporary data is omitted from rebuilt control data.

Abstract: An open block management apparatus, system, and method for non-volatile memory devices is disclosed herein, providing improved performance for namespace-based host applications. The namespace identifier is applied to determine the open blocks to which to direct data from storage commands. One benefit of the disclosed technique is fewer de-fragmentation operations and more efficient memory garbage collection. Another benefit is the ability to secure private allocations of physical memory without needing to assign a partition or implement hardware isolation.

Abstract: A black box device for a vehicle includes a data storage system for recording event data fed to the black box from various vehicle sensors. The data storage system includes a memory having memory cells and a controller in communication with the memory. The controller is configured to receive data and determine one or more memory cells as a destination for the data to be written. The controller is configured to determine a wear level of the memory cells and select a subset of program states of the memory cells based on the wear level; and program the memory cells using respective subsets of program states for each respective memory cell.

Abstract: The present disclosure generally relate to dynamically changing predictive latency related attributes to increase the deterministic window (DTWIN) of operation. The host device workload characteristics as well as the memory device's current condition provide valuable information for the duration of the DTWIN. If the memory device is near the end of life, then the DTWIN duration will be smaller. Additionally, if the workload from the host device is heavy, then the DTWIN duration will also be smaller. Rather than utilizing a fixed DTWIN duration based upon worst case scenarios for host device workload and memory device condition, dynamically adjusting the DTWIN duration based upon the workload and condition will provide a DTWIN duration that can gradually decrease over time from a much longer DTWIN duration than is currently available.

Abstract: A memory controller includes, in one embodiment, a memory interface and a dynamic stripe length manager circuit configured to receive a first weighted health factor associated with a first memory block of the memory, determine a first collective stripe length of the first memory block based on the first weighted health factor, set a first number of zones in the first memory block based on the first collective stripe length, monitor the memory to detect a trigger event that triggers a calculation of a second collective stripe length of the first memory block, the second collective stripe length being larger than the first collective stripe length, receive a second weighted health factor associated with the first memory block, determine the second collective stripe length based on the second weighted health factor, and set a second number of zones in the first memory block based on the second collective stripe length.

Abstract: A memory controller includes, in one embodiment, a memory interface and a dynamic stripe length manager circuit configured to receive a first weighted health factor associated with a first memory block of the memory, determine a first collective stripe length of the first memory block based on the first weighted health factor, set a first number of zones in the first memory block based on the first collective stripe length, monitor the memory to detect a trigger event that triggers a calculation of a second collective stripe length of the first memory block, the second collective stripe length being larger than the first collective stripe length, receive a second weighted health factor associated with the first memory block, determine the second collective stripe length based on the second weighted health factor, and set a second number of zones in the first memory block based on the second collective stripe length.

Abstract: This disclosure relates to an apparatus including a zone manager to manage memory allocation and behavior under a Zoned Namespaces (ZNS) implementation. The zone manager may include a monitor circuit, an evaluation circuit, and a signaling circuit. The monitor circuit is configured to monitor a zone metric for each zone of a non-volatile storage device. The evaluation circuit is configured to determine health for each zone based on the zone metric. The signaling circuit is configured to notify a host of the zone health for one or more zones in response to the zone metric for the zone(s) satisfying an alert threshold.

Abstract: A storage system and method for reducing read-retry duration are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to: receive a command from a host; and in response to an interruption in processing of the command: select a time for the host to retry the command, wherein the time is selected based on an expected host response time; and communicate the selected time to the host. Other embodiments are provided.

Abstract: A method and system for maintaining coherency between DMA and NVMe data paths are disclosed. As DMA requests are received in the PMR region, a device controller will translate these into NVMe commands with a dedicated queue that is hidden from a host that has higher priority than the corresponding host (NVMe) commands. The payload returned from an internally executed NVMe command is stored in a buffer used to complete the DMA request. As memory reads are submitted, the controller will mark corresponding LBA ranges for overlap, ensuring coherency between these reads and writes from other queues. Since the internal PMR queue has a higher priority than host-facing queues (e.g., NVMe), and the PMR is read-only, read coherency against host writes to the same region may be achieved.

Abstract: A storage system and method for enabling host-driven regional performance in memory are provided. In one embodiment, a method is provided comprising receiving a directive from a host device as to a preferred logical region of a non-volatile memory in a storage system; and based on the directive, modifying a caching policy specifying which pages of a logical-to-physical address map stored in the non-volatile memory are to be cached in a volatile memory of the storage system. Other embodiments are provided, such as modifying a garbage collection policy of the storage system based on information from the host device regarding a preferred logical region of the memory.

Abstract: An illustrative embodiment disclosed herein is an apparatus including a processor having programmed instructions that write data having mixed deletion characteristics sequentially to a plurality of data entries of a first physical erase block (PEB) in intermediate storage. The data having the mixed deletion characteristics includes first data having a first deletion characteristic. The processor has programmed instructions that maintain metadata in a plurality of metadata entries in a log. The metadata corresponds to the data having the mixed deletion characteristics. The processor has programmed instructions that identify, using the log, the first data having the first deletion characteristic and evacuate the first data having the first deletion characteristic to a second PEB in main memory.

Abstract: Technology is disclosed for reading non-volatile memory when a host does not need perfect data. By allowing the memory to return data with some errors, the data will be provided to the host much quicker. Therefore, in response to one or more host read commands, the memory system returns multiple copies of the data over time, progressively getting better so that later in time copies of the data have lower number of errors. The host decides when the error rate is good enough and stops the process (or ignores the rest of the results).

Abstract: The disclosure describes methods and systems for a storage device that includes one or more memory devices, where the memory devices store a second challenge question and a first response key. The system also includes an interface and a storage controller coupled to the interface and coupled to the memory devices. The storage controller generates an enable signal for enabling access to the memory devices. The system also includes a security module coupled to the storage controller and configured to send and receive challenge requests and challenge responses, where the security module includes a first challenge question and a second response key corresponding to each of the memory devices.

Abstract: A solid state device is disclosed comprising an array of memory units, an interface connected to the memory units, at least one arrangement to monitor a temperature of the solid state device and an arrangement to monitor low power mode statistics of the solid state device and compare the low power mode statistics to a critical usage point power threshold at a temperature measured, wherein the arrangement to monitor the low power mode statistics of the solid state device is further configured to change a power mode of the solid state device based upon the low power mode statistics.

Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit. The capacity of the media unit is divided into a plurality of zones. The controller is configured to make informed use of errors by update zone metadata to indicate one or more first logical block addresses were skipped and to indicate the next valid logical block address is available to store data. The controller is further configured to update zone metadata to recommend to the host device to reset one or more full zones, to recommend to the host device to transition one or more open zones to a full state, to alert the host device that one or more open zones have been transitioned to the full state, and to notify the host device of the writeable zone capacity of each of the plurality of zones.