Patents by Inventor Jui-Hsiang Pan
Jui-Hsiang Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9270181Abstract: An automatic adjusting device is provided, which is used for adjusting an output power of a power supply and comprises an automatic adjusting circuit. The automatic adjusting circuit includes a comparing unit and a programmable signal generating unit. The comparing unit compares a limiting level and a protection level and produces a comparison signal. The protection level limits the output power provided by the power supply. The programmable signal generating unit generates the protection level and adjusts the protection level according to the comparison signal for adjusting the output power. The programmable signal generating unit will adjust the protection level according to the limiting level. Thereby, the output power can be adjusted automatically without manual adjustment. Consequently, the cost can be reduced and the adjusting accuracy can enhanced.Type: GrantFiled: March 8, 2013Date of Patent: February 23, 2016Assignee: Infinno Technology Corp.Inventors: Jui-Hsiang Pan, Ming-Zhi Tzeng
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Publication number: 20130294116Abstract: An automatic adjusting device is provided, which is used for adjusting an output power of a power supply and comprises an automatic adjusting circuit. The automatic adjusting circuit includes a comparing unit and a programmable signal generating unit. The comparing unit compares a limiting level and a protection level and produces a comparison signal. The protection level limits the output power provided by the power supply. The programmable signal generating unit generates the protection level and adjusts the protection level according to the comparison signal for adjusting the output power. The programmable signal generating unit will adjust the protection level according to the limiting level. Thereby, the output power can be adjusted automatically without manual adjustment. Consequently, the cost can be reduced and the adjusting accuracy can enhanced.Type: ApplicationFiled: March 8, 2013Publication date: November 7, 2013Inventors: JUI-HSIANG PAN, MING-ZHI TZENG
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Patent number: 7663234Abstract: A package of a semiconductor device with a flexible wiring substrate and a method thereof are provided. The package of the semiconductor device includes a semiconductor substrate with at least one pad on a surface thereof, a bump bonded to the pad, an adhesive layer on the bump, and a flexible wiring substrate having at least one contact section being electrically connected with the bump by the adhesive layer. The present invention makes the flexible wiring substrate directly conductively attached onto the semiconductor substrate. The package size is shrunk and the cost down can be obtained.Type: GrantFiled: May 25, 2006Date of Patent: February 16, 2010Assignee: United Microelectronics Corp.Inventors: Joseph Sun, Kuang-Chih Cheng, Ming-Chieh Chen, Kevin Lee, Jui-Hsiang Pan
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Patent number: 7531381Abstract: The present invention provides a method for fabricating a quad flat no-lead package structure, comprising a chip carrier and at least a chip. The chip is disposed on the top surface of the chip carrier, while the back surface of the chip carrier includes a plurality of flat no-lead conductive leads as I/O pads of the chip carrier for the external circuitry. A plurality of pads, corresponding to bonding pads of the chip, is disposed on the top surface of the chip carrier. The aforementioned package structure can employ wiring bonding technology, flip chip technology or surface mount technology to attach the chip to the chip carrier.Type: GrantFiled: February 26, 2006Date of Patent: May 12, 2009Assignee: United Microelectronics Corp.Inventors: Jui-Hsiang Pan, Kuang-Shin Lee, Cheng-Kuang Sun
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Patent number: 7303400Abstract: A package of a semiconductor device with a flexible wiring substrate and a method thereof are provided. The package of the semiconductor device includes a semiconductor substrate with at least one pad on a surface thereof, a bump bonded to the pad, an adhesive layer on the bump, and a flexible wiring substrate having at least one contact section being electrically connected with the bump by the adhesive layer. The present invention makes the flexible wiring substrate directly conductively attached onto the semiconductor substrate. The package size is shrunk and the cost down can be obtained.Type: GrantFiled: January 27, 2005Date of Patent: December 4, 2007Assignee: United Microelectronics Corp.Inventors: Joseph Sun, Kuang-Chih Cheng, Ming-Chieh Chen, Kevin Lee, Jui-Hsiang Pan
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Patent number: 7291908Abstract: The present invention provides a QFN package structure, comprising a chip carrier and at least a chip. The chip is disposed on the top surface of the chip carrier, while the back surface of the chip carrier includes a plurality of flat no-lead conductive leads as I/O pads of the chip carrier for the external circuitry. A plurality of pads, corresponding to bonding pads of the chip, is disposed on the top surface of the chip carrier. The aforementioned package structure can employ wiring bonding technology, flip chip technology or surface mount technology to attach the chip to the chip carrier.Type: GrantFiled: August 13, 2004Date of Patent: November 6, 2007Assignee: United Microelectronics Corp.Inventors: Jui-Hsiang Pan, Kuang-Shin Lee, Cheng-Kuang Sun
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Publication number: 20060202333Abstract: A package of a semiconductor device with a flexible wiring substrate and a method thereof are provided. The package of the semiconductor device includes a semiconductor substrate with at least one pad on a surface thereof, a bump bonded to the pad, an adhesive layer on the bump, and a flexible wiring substrate having at least one contact section being electrically connected with the bump by the adhesive layer. The present invention makes the flexible wiring substrate directly conductively attached onto the semiconductor substrate. The package size is shrunk and the cost down can be obtained.Type: ApplicationFiled: May 25, 2006Publication date: September 14, 2006Applicant: UNITED MICROELECTRONICS CORP.Inventors: JOSEPH SUN, KUANG-CHIH CHENG, MING-CHIEH CHEN, KEVIN LEE, JUI-HSIANG PAN
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Publication number: 20060180860Abstract: An image sensor including an image sensing device layer, a silicon-on-insulator (SOI) layer, an optical device array and a substrate is provided. The SOI layer has a first surface and a second surface. The image sensing device layer is formed on the first surface of the SOI layer. The optical device array is formed on the second surface of the SOI layer. The substrate is disposed above the second surface of the SOI layer; the optical device array is disposed between the substrate and the SOI layer. An incident light coming from the outside environment, passes through the optical device array and the SOI layer, and is received by sensing devices formed in the image sensing device layer. In this manner, the probability of absorption or reflection of the incident light is reduced. Therefore, the sensing performance and the yield of the image sensor of the present invention is improved.Type: ApplicationFiled: March 16, 2006Publication date: August 17, 2006Inventors: Jui-Hsiang Pan, Cheng-Kuang Sun, Kuang-Chih Cheng, Kuang-Hsing Lee
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Patent number: 7091585Abstract: A process for fabricating a semiconductor device is provided. The process integrates a cutting film process into the front-end of semiconductor process. The cutting film is directly formed on the curved surface of the micro-lens or a passivation layer is formed on the micro-lens before covering the passivation layer with the cutting film. In addition to micro-particle contamination due to sawing, the process is able to simplify chip packaging and reduce the size of a photosensitive module.Type: GrantFiled: November 8, 2004Date of Patent: August 15, 2006Assignee: United MIcroelectronics Corp.Inventors: Cheng-Kuang Sun, Kuang Lee, Jui-Hsiang Pan
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Publication number: 20060131723Abstract: The present invention provides a method for fabricating a quad flat no-lead package structure, comprising a chip carrier and at least a chip. The chip is disposed on the top surface of the chip carrier, while the back surface of the chip carrier includes a plurality of flat no-lead conductive leads as I/O pads of the chip carrier for the external circuitry. A plurality of pads, corresponding to bonding pads of the chip, is disposed on the top surface of the chip carrier. The aforementioned package structure can employ wiring bonding technology, flip chip technology or surface mount technology to attach the chip to the chip carrier.Type: ApplicationFiled: February 26, 2006Publication date: June 22, 2006Inventors: Jui-Hsiang Pan, Kuang-Shin Lee, Cheng-Kuang Sun
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Patent number: 7060592Abstract: An image sensor comprising an image sensing device layer, a silicon-on-insulator (SOI) layer, an optical device array and a substrate is provided. The SOI layer has a first surface and a second surface. The image sensing device layer is formed on the first surface of the SOI layer. The optical device array is formed on the second surface of the SOI layer. The substrate is disposed above the second surface of the SOI layer and the optical device array is disposed between the substrate and the SOI layer. An incident light coming from the outside environment, passes through the optical device array and the SOI layer, and is received by sensing devices formed in the image sensing device layer. In this manner, the probability of absorption or reflection of the incident light is reduced. Therefore, the sensing performance and the yield of the image sensor of the present invention is improved.Type: GrantFiled: September 15, 2004Date of Patent: June 13, 2006Assignee: United Microelectronics Corp.Inventors: Jui-Hsiang Pan, Cheng-Kuang Sun, Kuang-Chih Cheng, Kuang-Shin Lee
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Publication number: 20060057764Abstract: An image sensor comprising an image sensing device layer, a silicon-on-insulator (SOI) layer, an optical device array and a substrate is provided. The SOI layer has a first surface and a second surface. The image sensing device layer is formed on the first surface of the SOI layer. The optical device array is formed on the second surface of the SOI layer. The substrate is disposed above the second surface of the SOI layer and the optical device array is disposed between the substrate and the SOI layer. An incident light coming from the outside environment, passes through the optical device array and the SOI layer, and is received by sensing devices formed in the image sensing device layer. In this manner, the probability of absorption or reflection of the incident light is reduced. Therefore, the sensing performance and the yield of the image sensor of the present invention is improved.Type: ApplicationFiled: September 15, 2004Publication date: March 16, 2006Inventors: Jui-Hsiang Pan, Cheng-Kuang Sun, Kuang-Chih Cheng, Kuang-Shin Lee
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Publication number: 20050161756Abstract: A package of a semiconductor device with a flexible wiring substrate and a method thereof are provided. The package of the semiconductor device includes a semiconductor substrate with at least one pad on a surface thereof, a bump bonded to the pad, an adhesive layer on the bump, and a flexible wiring substrate having at least one contact section being electrically connected with the bump by the adhesive layer. The present invention makes the flexible wiring substrate directly conductively attached onto the semiconductor substrate. The package size is shrunk and the cost down can be obtained.Type: ApplicationFiled: January 27, 2005Publication date: July 28, 2005Applicant: UNITED MICROELECTRONICS CORP.Inventors: Joseph Sun, Kuang-Chih Cheng, Ming-Chieh Chen, Kevin Lee, Jui-Hsiang Pan
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Patent number: 6921681Abstract: A process for fabricating a semiconductor device is provided. The process integrates a cutting film process into the front-end of semiconductor process. The cutting film is directly formed on the curved surface of the micro-lens or a passivation layer is formed on the micro-lens before covering the passivation layer with the cutting film. In addition to micro-particle contamination due to sawing, the process is able to simplify chip packaging and reduce the size of a photosensitive module.Type: GrantFiled: October 7, 2003Date of Patent: July 26, 2005Assignee: United Microelectronics Corp.Inventors: Cheng-Kuang Sun, Kuang-Shin Lee, Jui-Hsiang Pan
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Publication number: 20050095739Abstract: A process for fabricating a semiconductor device is provided. The process integrates a cutting film process into the front-end of semiconductor process. The cutting film is directly formed on the curved surface of the micro-lens or a passivation layer is formed on the micro-lens before covering the passivation layer with the cutting film. In addition to micro-particle contamination due to sawing, the process is able to simplify chip packaging and reduce the size of a photosensitive module.Type: ApplicationFiled: November 8, 2004Publication date: May 5, 2005Inventors: Cheng-Kuang Sun, Kuang-Shin Lee, Jui-Hsiang Pan
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Publication number: 20050073055Abstract: The present invention provides a QFN package structure, comprising a chip carrier and at least a chip. The chip is disposed on the top surface of the chip carrier, while the back surface of the chip carrier includes a plurality of flat no-lead conductive leads as I/O pads of the chip carrier for the external circuitry. A plurality of pads, corresponding to bonding pads of the chip, is disposed on the top surface of the chip carrier. The aforementioned package structure can employ wiring bonding technology, flip chip technology or surface mount technology to attach the chip to the chip carrier.Type: ApplicationFiled: August 13, 2004Publication date: April 7, 2005Inventors: Jui-Hsiang Pan, Kuang-Shin Lee, Cheng-Kuang Sun
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Publication number: 20050074916Abstract: A process for fabricating a semiconductor device is provided. The process integrates a cutting film process into the front-end of semiconductor process. The cutting film is directly formed on the curved surface of the micro-lens or a passivation layer is formed on the micro-lens before covering the passivation layer with the cutting film. In addition to micro-particle contamination due to sawing, the process is able to simplify chip packaging and reduce the size of a photosensitive module.Type: ApplicationFiled: October 7, 2003Publication date: April 7, 2005Inventors: Cheng-Kuang Sun, Kuang-Shin Lee, Jui-Hsiang Pan
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Patent number: 6583484Abstract: A method for manufacturing a photodiode CMOS image sensor. A first well and a second well are formed in a first type substrate. An isolation layer is formed over the first well and the second well. At the same time, an isolation layer is formed over another region to pattern out an active region for forming the photodiode. A protective ring layer is formed over the peripheral area of the photodiode active region. A first gate structure and a second gate structure are formed above the first well and the second well respectively. A first type source/drain region and a second type source/drain region are formed in the first well and the second well respectively. Concurrently, a second type heavily doped layer is formed in the first type substrate inside the area enclosed by the protective ring layer. A high-energy ion implantation is carried out to form a second type lightly doped layer in the first type substrate just outside the second type heavily doped layer.Type: GrantFiled: March 1, 2001Date of Patent: June 24, 2003Assignee: United Microelectronics Corp.Inventors: Jui-Hsiang Pan, Ming-I Chen
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Patent number: 6573118Abstract: The surface of the semiconductor wafer includes a silicon substrate containing first-type dopants, a well of first-type dopants positioned in a predetermined region on the substrate, a photo diode positioned on the semiconductor wafer and comprising an active region positioned on the surface of the well, the active region being used to form a MOS transistor of second-type dopants, and an insulation layer positioned on the surface of the substrate surrounding a predetermined photo sensor, the photo sensor positioned beside the well. A first ion implantation process is performed to form a first doped region of second-type dopants on the surface of the photo sensor. A second ion implantation process is then performed to form a second doped region of second-type dopants inside the photo sensor.Type: GrantFiled: June 4, 2001Date of Patent: June 3, 2003Assignee: United Microelectronics Corp.Inventor: Jui-Hsiang Pan
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Patent number: 6552320Abstract: An image sensor structure. A first PN photodiode is located in a photo-sensing region of a substrate. A second PN photodiode is located in the substrate above the first PN photodiode. An N-type terminal of the first PN photodiode connects to a source/drain region of a first transistor. A contact is coupled with the second PN photodiode. The contact connects to a gate of a second transistor.Type: GrantFiled: July 7, 1999Date of Patent: April 22, 2003Assignee: United Microelectronics Corp.Inventor: Jui-Hsiang Pan