Abstract: The surface of a semiconductor wafer comprises a silicon substrate and a well positioned in a predetermined area just under the surface of the substrate. A photo diode comprises a MOS transistor positioned on the surface of the well, a photo sensor positioned beside the well and electrically connected to the MOS transistor, and an insulation layer positioned on the surface of the substrate surrounding the photo sensor. The photo sensor comprises a first doped region positioned on the surface of the photo sensor, and a second doped region positioned between the first doped region and the insulation layer, a portion of the second doped region at least partially under the insulation layer. The dopant density of the second doped region is less than that of the first doped region, and the second doped region functions to reduce the electrical field around the first doped region so as to reduce the leakage current.

Abstract: The present invention relates to a method of forming a photo diode on a semiconductor wafer. The method comprises forming a pad silicon oxide layer on the substrate and a silicon nitride layer on the pad silicon oxide layer. Then, remove portion of the silicon nitride layer over which the remaining silicon nitride layer defines a photo sensor area and at least one dummy active area on the pad silicon oxide layer. Next, each dummy active area are positioned surrounding the photo sensor area with a narrow slot in between which is not covered by the silicon nitride layer. Next, perform a thermal oxidation process over the slot to form a field oxide layer, the dummy active area is used to reduce the thickness of the field oxide layer in the slot. Then, remove the remaining silicon nitride layer by using a wet etching process.

Abstract: The present invention is related to a MOS ESD protection circuit with embedded well diodes.

Abstract: A CMOS sensor structure and method of manufacture employs conventional semiconductor techniques. The CMOS sensor has a silicon nitride layer in the substrate formed by a high-energy implant technique. The silicon nitride layer is formed below the P-N junction created by a sensing region and the substrate. Utilizing the difference in refractive indexes between the silicon nitride layer, the substrate material (P-N junction area) and a passivation dielectric layer, the silicon nitride layer becomes an effective light-reflecting buffer layer. Hence, the effective interaction length of light ray is increased and the possibility of light absorption by the substrate is reduced.

Abstract: The electrostatic discharge protection circuit provided by the present invention is an ESD protection circuit with field oxide device, moreover the provided ESD protection circuit uses both PN diode and parasitic bipolar to conduct charger from the input pad of integrated circuit. The equivalent circuit of the invention is equal to the equivalent circuit of conventional FOD kind ESD protection circuit, and the basic structure also is similar to the structure of a conventional ESD protection circuit. The main characteristic of the invention is that deep junction is used to increase junction cross-section area of each junction, especially a deep drain-like junction. In other words, deep junctions are used in the following cases: Drain-like region of field oxide device, diode between VDD and VSS, and diode between the VDD and the pad.

Abstract: A CMOS sensor and a method of manufacturing a CMOS sensor. One major aspect of this invention is the use of a high-energy ion implantation to form a silicon nitride layer underneath the sensing region. Then, N-type dopants are implanted to form an N-type region above the silicon nitride layer within the substrate. Thereafter, a P-type epitaxial layer is formed above the substrate, thereby forming an intrinsic depletion region between the epitaxial layer and the N-doped region. The intrinsic depletion region is a light-sensitive area where light energy is converted into electrical signal. Height of the intrinsic depletion region can be adjusted through controlling the depth of the implant in the N-doped region.

Abstract: A structure of a photo diode and a method of manufacturing a photo diode comprise the steps of providing a substrate having an isolation region and a device region. A doped region is formed adjacent to the isolation region in the substrate by performing an ion implantation step and an annealing step. Next, a protective layer utilized to prevent the plasma damage is formed on the substrate and the isolation region, and an inter-layer dielectric layer is formed on the protective layer. Thereafter, a contact hole is formed to expose a portion of the doped region by patterning the inter-layer dielectric layer and the protective layer, and a contact plug is formed by filling the contact hole with a conductive material.

Abstract: This invention provides a method of simultaneously forming a photo diode and a CMOS transistor on a semiconductor wafer. The semiconductor wafer comprises a P-type substrate. The surface of the P-type substrate comprises at least one N-channel MOS area for forming an NMOS transistor of the CMOS transistor, a P-channel MOS area for forming a PMOS transistor of the CMOS transistor, and a photo sensing area for forming a photo diode. The method comprises an ion implantation process to form a P-type well in the NMOS area, and an ion implantation process to form a N-type doped area in a predetermined area on the surface of the photo sensing area and also to form a N-type well of the PMOS transistor in the PMOS area. The dopants in the N-type doped area will interact with the neighboring P-type substrate to form a depletion region which fills the P-type substrate within the photo sensing area but outside the predetermined area.

Abstract: A method of forming gate oxide layers. A first and a second poly-silicon gates are formed over a substrate. An amorphous silicon layer is formed on the first poly-silicon gate, followed by oxidizing the amorphous silicon layer and the second poly-silicon gate. A poly-silicon layer is formed on the gate oxide layers, devices with different capacitance are formed.

Abstract: The present invention provides a method of simultaneously forming a photo diode and a CMOS transistor on a semiconductor wafer. The surface of the semiconductor wafer comprising a P-type substrate with at least one N-channel MOS area for forming a NMOS transistor of the CMOS transistor, and a photo sensing area for forming the photo diode. The method employs a first ion implantation process to form a P-type well in the NMOS area. Next, a second ion implantation process simultaneously forms a first N-type doped area in a predetermined area of the photo sensing area and a lightly doped drain of the NMOS transistor on the surface of the P-type well of the N-channel MOS area. Finally, a third ion implantation process forms a second N-type doped area in part of the surface of the photo sensing area, and forms the source and drain of the NMOS in the P-type well of the NMOS. The second N-type doped area and the first N-type doped area of the photo sensing area are at least partially overlapping.

Abstract: A method for avoiding interference in a CMOS sensor. A substrate at least comprising a CMOS sensor, an interconnect layer and an inter-layer dielectric layer thereon is provided. A passivation layer is formed over the substrate. A photolithography and etching process is performed to remove a part of the passivation layer and a part of the inter-layer dielectric layer above a sensor region of the CMOS sensor. The sensor region is thus exposed. An oxide layer is formed on the exposed sensor region. A micro-lens is formed on the oxide layer.