Abstract: A photodetector pixel cell is proposed by the invention. Herein, the presented pixel cell comprises a diode region and a circuit region, and is enclosed by isolation. Moreover, the doped region is existed inside both regions. The structure of the presented pixel cell comprises following characteristics: First, the first well is only located inside the circuit region, where the conductive type of the first well is opposite to the conductive type of the doped region. Second, the second well is located inside the diode region and is contiguous to the isolation, where the conductive type of the second well is equal to that of the doped region. Third, the doped region is not contiguous to the second well, they are separated by uncovered surface part of the substrate. Fourth, the doped region and the substrate provide the diode.

Abstract: A method of fabricating a MOS sensor is described. A P-doped region extending into a substrate is formed. A stacked polysilicon structure is formed over the P-doped region. Ions are implanted into the substrate to form an N-doped region extending shallowly into the P-doped region, the stacked polysilicon structure serving as an implantation buffer layer. The stacked polysilicon structure are patterned and etched to form a stacked polysilicon ring over the N-doped region. A metal line is formed for electrically connecting the stacked polysilicon ring with a gate of a MOS transistor.

Abstract: The present invention relates to a photo diode and its method of formation. The photo diode comprises a photo sensor area positioned in a predetermined region on the substrate, and a dielectric area positioned on the substrate surrounding the photo sensor area. The dielectric area comprises a field oxide layer covering a portion of the dielectric area and at least one dummy active area surrounding the photo sensor area, and a narrow slot of the field oxide layer exists between each dummy active area and the photo sensor area. In the formation of the dielectric area, the dummy active area reduces the thickness of the field oxide layer in the slot and decreases the stress causes by the field oxide layer. So the leakage current of the photo diode in unlighted status can be decreased and improve the signal to noise ratio.

Abstract: A method of fabricating a MOS sensor is described. A P-doped region extending into a substrate is formed. A stacked polysilicon structure is formed over the P-doped region. Ions are implanted into the substrate to form an N-doped region extending shallowly into the P-doped region, the stacked polysilicon structure serving as an implantation buffer layer. The stacked polysilicon structure are patterned and etched to form a stacked polysilicon ring over the N-doped region. A metal line is formed for electrically connecting the stacked polysilicon ring with a gate of a MOS transistor.

Abstract: An electrostatic discharge protection apparatus. Drift regions of source regions and drain regions in the conventional PMOS transistor and NMOS transistor are removed to avoid spike discharge. In addition, a P-type pocket region are formed at peripheries of the drain region and the source region of an NMOS transistor, and N-type pocket regions are formed at peripheries of the drain region and the source region of a PMOS transistor.

Abstract: The present invention proposes a die seal ring. The provided die seal ring is formed on a substrate and is used to encompass a die by locating between the die and adjacent scribe lines. Moreover, the provided die seal ring comprises a plurality of dielectric layers and a plurality of metal structures, wherein any metal structure is not overlapped with other metal structures. Moreover, dielectric layers are located on the substrate in sequence, and each metal structure is stacked by one metal ring and one metal plug. In addition, any metal ring is located on a dielectric layer and is covered by another dielectric layer, and metal rings of different metal structures are located on different dielectric layers. Further, any metal plug is located in the dielectric layers and is used to connect the metal ring to the substrate. Of course, if the aspect ratio of any metal plug is too large to be properly formed, an appendant metal ring is used to reduce the aspect ration of the metal plug.

Abstract: A silicon chip built-in inductor structure. The structure at least includes a substrate, a plurality of active devices on the substrate, a dielectric layer with a planarized upper surface and an inductor device. The substrate can be divided into an active device region and a region containing grid-like field oxide devices. The grid-like field oxide region has a plurality of field oxide layers, a plurality of first-type-ion-doped regions underneath the field oxide layers and a plurality of second-type-ion-doped region in the substrate between the various field oxide layers. A plurality of junction regions are formed between the first-type-ion-doped regions and the second-type-ion-doped regions. The junction regions impede the flow of an eddy current along a prescribed direction. A dielectric layer is formed over the substrate covering the active devices and the field oxide devices. The inductor device is formed on the dielectric layer above the field oxide devices.

Abstract: A high voltage electrostatic discharge protection circuit having a virtual N+ region additionally formed according to the invention is disclosed. Due to the formation of the virtual N+ region, the distance between the base and collector of a parasitic bipolar junction transistor is greatly increased to keep its holding voltage always greater than its operation voltage, thereby preventing a problem of latch up.

Abstract: A photodiode. A second conductive type heavily doped region is located in a first conductive type doped substrate, and a dopant concentration of the second conductive type heavily doped region is larger than that of the first conductive type doped substrate. A dummy isolation is at a periphery of the second conductive type heavily doped region. A first conductive type heavily doped region is located at a periphery of the dummy isolation layer in the first conductive type doped substrate. A dopant concentration of the first conductive type heavily doped region is larger than that of the first conductive type substrate. An isolation layer is located at a periphery of the first conductive type doped region with a width much larger than that of the dummy isolation layer.

Abstract: The surface of the semiconductor wafer includes a silicon substrate containing first-type dopants, a well of first-type dopants positioned in a predetermined region on the substrate, a photo diode positioned on the semiconductor wafer and comprising an active region positioned on the surface of the well, the active region being used to form a MOS transistor of second-type dopants, and an insulation layer positioned on the surface of the substrate surrounding a predetermined photo sensor, the photo sensor positioned beside the well. A first ion implantation process is performed to form a first doped region of second-type dopants on the surface of the photo sensor. A second ion implantation process is then performed to form a second doped region of second-type dopants inside the photo sensor.

Abstract: The present invention is about a CMOS image sensor device. A CMOS image device has a first MOS device acting as a source follower of an active pixel, a second MOS device acting as a row select of the active pixel. An amorphous silicon layer acting as a photo-diode area for collecting incident light. The amorphous silicon layer has both N-type and P-type dopants.

Abstract: The present invention is related to a method for forming a CMOS image sensor device. A CMOS image device has a first MOS device acting as a source follower of an active pixel, a second MOS device acting as a row select of the active pixel. An amorphous silicon layer acts as a photo-diode area for collecting incident light over the first MOS device and the second MOS device. The amorphous silicon layer has both N-type and P-type dopants.

Abstract: A method for manufacturing a photodiode CMOS image sensor. A first well and a second well are formed in a first type substrate. An isolation layer is formed over the first well and the second well. At the same time an isolation layer is formed over another region to pattern out an active region for forming the photodiode. A protective ring layer is formed over the peripheral area of the photodiode active region. A first gate structure and a second gate structure are formed above the first well and the second well respectively. A first type source/drain region and a second type source/drain region are formed in the first well and the second well respectively. Concurrently, a second type heavily doped layer is formed in the first type substrate inside the area enclosed by the protective ring layer. A high-energy ion implantation is carried out to form a second type lightly doped layer in the first type substrate just outside the second type heavily doped layer.

Abstract: A method for manufacturing a photodiode CMOS image sensor. A first well and a second well are formed in a first type substrate. An isolation layer is formed over the first well and the second well. At the same time, an isolation layer is formed over another region to pattern out an active region for forming the photodiode. A protective ring layer is formed over the peripheral area of the photodiode active region. A first gate structure and a second gate structure are formed above the first well and the second well respectively. A first type source/drain region and a second type source/drain region are formed in the first well and the second well respectively. Concurrently, a second type heavily doped layer is formed in the first type substrate inside the area enclosed by the protective ring layer. A high-energy ion implantation is carried out to form a second type lightly doped layer in the first type substrate just outside the second type heavily doped layer.

Abstract: A method for fabricating a CMOS image sensor is disclosed. The CMOS sensor includes the portions of sensor photo-diode array NMOS and PMOS. In the method, partial steps involving implantation for image sensor fabrication are implemented at different times with the fabrication of NMOS. The method is compatible with the present process only to add a mask for patterning sensor implantation and to modify some traditional patterns of masks. The doses of the field region within the region of sensor photo-diode array can be implemented separately and are not subject to higher dopants for NMOS in the present fabrication. Thus, the doses for the sensor photo-diode array can be adjusted to meet the requirements of isolation and low dark current for the image sensor.

Abstract: A semiconductor wafer is provided. The semiconductor wafer comprises a silicon substrate containing first-type dopants, a well of first-type dopants positioned in a predetermined region on the substrate, and a photo diode positioned on the semiconductor wafer. The photo diode comprises an active region positioned on the surface of the well. The active region is used to form a MOS transistor of second-type dopants. An insulation layer is positioned on the surface of the substrate and surrounds a predetermined photo sensor, the photo sensor being positioned beside the well. Following this, a first ion implantation process is performed to form a first doped region of second-type dopants on the surface of the photo sensor. A second ion implantation process is then performed to form a second doped region of second-type dopants inside the photo sensor. The second doped region is positioned under the first doped region, and the dopant density of the second doped region is less than that of the first doped region.

Abstract: A CMOS structure having a silicon dioxide outer ring around the sense region. The CMOS sense structure has a substrate, a n− region, a n+ region, an isolation region, a field implant region and a silicon dioxide outer ring region. The n− region is formed in the substrate, and the n+ region is formed within the n− region. The isolation region is formed in the substrate next to the edge of the n− region. The field implant region is formed under the isolation region. The silicon dioxide outer ring region is formed over the n− region, a portion of the isolation region and a portion of the n+ region. The silicon dioxide outer ring can prevent surface leakage that is caused by etching and lengthening the distance from the n− region to the field implant region so that edge junction leakage is reduced.

Abstract: A CMOS structure having a silicon dioxide outer ring around the sense region. The CMOS sense structure has a substrate, a n− region, a n+ region, an isolation region, a field implant region and a silicon dioxide outer ring region. The n− region is formed in the substrate, and the n+ region is formed within the n− region. The isolation region is formed in the substrate next to the edge of the n− region. The field implant region is formed under the isolation region. The silicon dioxide outer ring region is formed over the n− region, a portion of the isolation region and a portion of the n+ region. The silicon dioxide outer ring can prevent surface leakage that is caused by etching and lengthening the distance from the n− region to the field implant region so that edge junction leakage is reduced.

Abstract: This invention provides a method of forming a CMOS image sensor. The image sensor is formed in a predetermined region of a semiconductor wafer covered with a P-type substrate. The wafer comprises at least one N-channel area for forming one NMOS transistor and a sensor area for forming a photo-diode sensor. At least one gate electrode in the N-channel area is formed first. A first ion-implantation is performed to form a lightly doped drain (LDD) layer in predetermined areas on the surface of the P-type substrate in the N-channel area next to the gate electrode. A second ion-implantation is performed to form a heavy doped drain (HDD) layer in another predetermined area on the surface of the substrate in the N-channel area next to the LDD. A third ion-implantation is performed to form a doped layer with phosphorus as the major dopant on the surface of the substrate in the sensor area.

Abstract: A high-voltage electrostatic discharge protection circuit according to the invention has the following structure. A first high-voltage N-well region, a first high-voltage P-well region, a second high-voltage N-well region and a second high-voltage P-well region are adjacent to each other. A PMOS transistor is formed on the first high-voltage N-well region and has its source electrically connected to a high voltage and its drain electrically connected to an input/output pad. A first isolation region is formed between the first high-voltage N-well region and the first high-voltage P-well region and electrically connected to the drain of the PMOS transistor. A first N+-type region is formed between the first high-voltage P-well region and the second high-voltage N-well region, adjacent to the first isolation region and electrically connected to the input/output pad.