Patents by Inventor Jui Hsieh Lai

Jui Hsieh Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10161875
    Abstract: A bio-chip package comprises a substrate a first layer over the substrate comprising an image sensor. The bio-chip package also comprises a second layer over the first layer. The second layer comprises a waveguide system a grating coupler. The bio-chip package also comprises a third layer arranged to accommodate a fluid between a first-third layer portion and a second-third layer portion, and to allow the fluid to pass from a first side of the third layer to a second side of the third layer. The third layer comprises a material having a predetermined transparency with respect to a wavelength of a received source light, the waveguide system is configured to direct the received source light to the grating coupler, and the image sensor is configured to determine a change in the wavelength of the source light caused by a coupling between the source light and the fluid.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui Hsieh Lai, Ying-Hao Kuo
  • Patent number: 10157901
    Abstract: A semiconductor device includes a first chip, a dielectric layer over the first chip, and a second chip over the dielectric layer. A conductive layer is embedded in the dielectric layer and is electrically coupled to the first chip and the second chip. The second chip includes an optical component. The first chip and the second chip are arranged on opposite sides of the dielectric layer in a thickness direction of the dielectric layer.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui Hsieh Lai, Ying-Hao Kuo, Kuo-Chung Yee
  • Patent number: 10061079
    Abstract: A method of making a grating in a waveguide includes forming a waveguide material over a substrate, the waveguide material having a thickness less than or equal to about 100 nanometers (nm). The method further includes forming a photoresist over the waveguide material and patterning the photoresist. The method further includes forming a first set of openings in the waveguide material through the patterned substrate and filling the first set of openings with a metal material.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: August 28, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui Hsieh Lai, Ying-Hao Kuo
  • Publication number: 20180136139
    Abstract: A bio-chip package comprises a substrate a first layer over the substrate comprising an image sensor. The bio-chip package also comprises a second layer over the first layer. The second layer comprises a waveguide system a grating coupler. The bio-chip package also comprises a third layer arranged to accommodate a fluid between a first-third layer portion and a second-third layer portion, and to allow the fluid to pass from a first side of the third layer to a second side of the third layer. The third layer comprises a material having a predetermined transparency with respect to a wavelength of a received source light, the waveguide system is configured to direct the received source light to the grating coupler, and the image sensor is configured to determine a change in the wavelength of the source light caused by a coupling between the source light and the fluid.
    Type: Application
    Filed: December 28, 2017
    Publication date: May 17, 2018
    Inventors: Jui Hsieh Lai, Ying-Hao Kuo
  • Publication number: 20180138056
    Abstract: In some embodiments, the present disclosure relates to a package for holding a plurality of integrated circuits. The package includes a first conductive pad over a first chip and a second conductive pad over a second chip. A molding structure surrounds the first chip and the second chip. A first passivation layer is over the first chip and the second chip, and a conductive structure is over the first passivation layer. The conductive structure is coupled to the first conductive pad. A second passivation layer is over the conductive structure. The first passivation layer and the second passivation layer have sidewalls defining an aperture that is directly over an optical element within the second chip and that extends through the first passivation layer and the second passivation layer.
    Type: Application
    Filed: December 27, 2017
    Publication date: May 17, 2018
    Inventors: Wan-Yu Lee, Chun-Hao Tseng, Jui Hsieh Lai, Tien-Yu Huang, Ying-Hao Kuo, Kuo-Chung Yee
  • Publication number: 20180061818
    Abstract: A semiconductor device includes a first chip, a dielectric layer over the first chip, and a second chip over the dielectric layer. A conductive layer is embedded in the dielectric layer and is electrically coupled to the first chip and the second chip. The second chip includes an optical component. The first chip and the second chip are arranged on opposite sides of the dielectric layer in a thickness direction of the dielectric layer.
    Type: Application
    Filed: October 30, 2017
    Publication date: March 1, 2018
    Inventors: Jui Hsieh Lai, Ying-Hao Kuo, Kuo-Chung Yee
  • Patent number: 9865481
    Abstract: A package for holding a plurality of heterogeneous integrated circuits includes a first chip having a first conductive pad and a first substrate including a first semiconductor, and a second chip having a second conductive pad and a second substrate including a second semiconductor. The second semiconductor is different from the first semiconductor. The package also includes a molding structure in which the first chip and the second chip are embedded, a conductive structure over the first chip and conductively coupled to the first conductive pad and over the second chip and conductively coupled to the second conductive pad, and a passivation layer over the conductive structure. The passivation layer comprises an opening defined therein which exposes a portion of the second chip.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: January 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Yu Lee, Chun-Hao Tseng, Jui Hsieh Lai, Tien-Yu Huang, Ying-Hao Kuo, Kuo-Chung Yee
  • Patent number: 9857309
    Abstract: A bio-chip package comprises a substrate a first layer over the substrate comprising an image sensor. The bio-chip package also comprises a second layer over the first layer. The second layer comprises a waveguide system a grating coupler. The bio-chip package also comprises a third layer arranged to accommodate a fluid between a first-third layer portion and a second-third layer portion, and to allow the fluid to pass from a first side of the third layer to a second side of the third layer. The third layer comprises a material having a predetermined transparency with respect to a wavelength of a received source light, the waveguide system is configured to direct the received source light to the grating coupler, and the image sensor is configured to determine a change in the wavelength of the source light caused by a coupling between the source light and the fluid.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui Hsieh Lai, Ying-Hao Kuo
  • Patent number: 9806069
    Abstract: A semiconductor device includes a first chip, a dielectric layer over the first chip, and a second chip over the dielectric layer. A conductive layer is embedded in the dielectric layer and is electrically coupled to the first chip and the second chip. The second chip includes an optical component. The first chip and the second chip are arranged on opposite sides of the dielectric layer in a thickness direction of the dielectric layer.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: October 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui Hsieh Lai, Ying-Hao Kuo, Kuo-Chung Yee
  • Patent number: 9799528
    Abstract: An apparatus includes a package structure. The package structure includes a chip, a conductive structure over the chip, a molding structure surrounding and underneath the chip, and a first passivation layer over the conductive structure. The chip includes an optical component and a chip conductive pad. The conductive structure is electrically coupled to the chip conductive pad. The conductive structure has a planar portion substantially in parallel with an upper surface of the chip. The first passivation layer has a first opening defined therein. The first opening exposes a portion of the planar portion. The package structure is configured to receive an electrical coupling through the first opening in the first passivation layer.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: October 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yu Lee, Chun-Hao Tseng, Jui Hsieh Lai, Tien-Yu Huang, Ying-Hao Kuo, Kuo-Chung Yee
  • Publication number: 20170160470
    Abstract: A method of making a grating in a waveguide includes forming a waveguide material over a substrate, the waveguide material having a thickness less than or equal to about 100 nanometers (nm). The method further includes forming a photoresist over the waveguide material and patterning the photoresist. The method further includes forming a first set of openings in the waveguide material through the patterned substrate and filling the first set of openings with a metal material.
    Type: Application
    Filed: February 20, 2017
    Publication date: June 8, 2017
    Inventors: Jui Hsieh Lai, Ying-Hao Kuo
  • Patent number: 9575249
    Abstract: A method of making a grating in a waveguide includes forming a waveguide material over a substrate, the waveguide material having a thickness less than or equal to about 100 nanometers (nm). The method further includes forming a photoresist over the waveguide material and patterning the photoresist. The method further includes forming a first set of openings in the waveguide material through the patterned substrate and filling the first set of openings with a metal material.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui Hsieh Lai, Ying-Hao Kuo
  • Publication number: 20170033094
    Abstract: An apparatus includes a package structure. The package structure includes a chip, a conductive structure over the chip, a molding structure surrounding and underneath the chip, and a first passivation layer over the conductive structure. The chip includes an optical component and a chip conductive pad. The conductive structure is electrically coupled to the chip conductive pad. The conductive structure has a planar portion substantially in parallel with an upper surface of the chip. The first passivation layer has a first opening defined therein. The first opening exposes a portion of the planar portion. The package structure is configured to receive an electrical coupling through the first opening in the first passivation layer.
    Type: Application
    Filed: October 14, 2016
    Publication date: February 2, 2017
    Inventors: Wan-Yu Lee, Chun-Hao Tseng, Jui Hsieh Lai, Tien-Yu Huang, Ying-Hao Kuo, Kuo-Chung Yee
  • Patent number: 9530673
    Abstract: An approach is provided for aligning and leveling a chip package portion. The approach involves filling, at least partially, a reservoir formed between a first sidewall portion having a first slanted surface and a second sidewall portion having a second slanted surface with a fluid. The approach also involves placing a chip package portion into the reservoir. The approach further involves draining the fluid from the reservoir to cause the chip package portion to align with respect to a center of the reservoir. The chip package portion aligns with respect to the center of the reservoir and levels based on a relationship between the chip package portion, an angle of the first slanted surface, an angle of the second slanted surface, and the fluid. The chip package portion is secured in the aligned and leveled state by a molding compound.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui Hsieh Lai, Ying-Hao Kuo, Kuo-Chung Yee
  • Publication number: 20160358900
    Abstract: A semiconductor device includes a first chip, a dielectric layer over the first chip, and a second chip over the dielectric layer. A conductive layer is embedded in the dielectric layer and is electrically coupled to the first chip and the second chip. The second chip includes an optical component. The first chip and the second chip are arranged on opposite sides of the dielectric layer in a thickness direction of the dielectric layer.
    Type: Application
    Filed: August 22, 2016
    Publication date: December 8, 2016
    Inventors: Jui Hsieh Lai, Ying-Hao Kuo, Kuo-Chung Yee
  • Publication number: 20160349183
    Abstract: A bio-chip package comprises a substrate a first layer over the substrate comprising an image sensor. The bio-chip package also comprises a second layer over the first layer. The second layer comprises a waveguide system a grating coupler. The bio-chip package also comprises a third layer arranged to accommodate a fluid between a first-third layer portion and a second-third layer portion, and to allow the fluid to pass from a first side of the third layer to a second side of the third layer. The third layer comprises a material having a predetermined transparency with respect to a wavelength of a received source light, the waveguide system is configured to direct the received source light to the grating coupler, and the image sensor is configured to determine a change in the wavelength of the source light caused by a coupling between the source light and the fluid.
    Type: Application
    Filed: August 8, 2016
    Publication date: December 1, 2016
    Inventors: Jui Hsieh Lai, Ying-Hao Kuo
  • Publication number: 20160343697
    Abstract: A package for holding a plurality of heterogeneous integrated circuits includes a first chip having a first conductive pad and a first substrate including a first semiconductor, and a second chip having a second conductive pad and a second substrate including a second semiconductor. The second semiconductor is different from the first semiconductor. The package also includes a molding structure in which the first chip and the second chip are embedded, a conductive structure over the first chip and conductively coupled to the first conductive pad and over the second chip and conductively coupled to the second conductive pad, and a passivation layer over the conductive structure. The passivation layer comprises an opening defined therein which exposes a portion of the second chip.
    Type: Application
    Filed: July 29, 2016
    Publication date: November 24, 2016
    Inventors: Wan-Yu Lee, Chun-Hao Tseng, Jui Hsieh Lai, Tien-Yu Huang, Ying-Hao Kuo, Kuo-Chung Yee
  • Patent number: 9478475
    Abstract: An apparatus includes a package structure. The package structure includes a chip, a conductive structure over the chip, a molding structure surrounding and underneath the chip, and a first passivation layer over the conductive structure. The chip includes an optical component and a chip conductive pad. The conductive structure is electrically coupled to the chip conductive pad. The conductive structure has a planar portion substantially in parallel with an upper surface of the chip. The first passivation layer has a first opening defined therein. The first opening exposes a portion of the planar portion. The package structure is configured to receive an electrical coupling through the first opening in the first passivation layer.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: October 25, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yu Lee, Chun-Hao Tseng, Jui Hsieh Lai, Tien-Yu Huang, Ying-Hao Kuo, Kuo-Chung Yee
  • Patent number: 9478939
    Abstract: An embodiment is a semiconductor device comprising an optical device over a first substrate, a vertical waveguide on a top surface of the optical device, the vertical waveguide having a first refractive index, and a capping layer over the vertical waveguide, the capping layer configured to be a lens for the vertical waveguide and the capping layer having a second refractive index.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: October 25, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui Hsieh Lai, Ying-Hao Kuo, Hai-Ching Chen, Tien-I Bao
  • Patent number: 9459144
    Abstract: An optical spectroscopy device includes a first cladding layer is positioned over a photodetector. An optical core region is over the first cladding layer where the optical core region is configured to receive a light beam. The optical core region includes a first grating having a first pitch where the first pitch is positioned to direct a first wavelength of the light beam to a first portion of the photodetector. The optical core region further includes a second grating having a second pitch where the second grating is positioned to direct a second wavelength of the light beam to a second portion of the photodetector. The first pitch is different from the second pitch, the first wavelength is different from the second wavelength, and the first portion of the photodetector is different from the second portion of the photodetector. Additionally, a second cladding layer is over the optical core region.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: October 4, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui Hsieh Lai, Ying-Hao Kuo