Abstract: A memory cell structure, including a substrate having a via therein bound at first and second ends thereof by electrodes. The via is coated on side surfaces thereof with GST material defining a core that is hollow or at least partially filled with material, e.g., germanium or dielectric material. One or more of such memory cell structures may be integrated in a phase change memory device. The memory cell structure can be fabricated in a substrate containing a via closed at one end thereof with a bottom electrode, by conformally coating GST material on sidewall surface of the via and surface of the bottom electrode enclosing the via, to form an open core volume bounded by the GST material, optionally at least partially filling the open core volume with germanium or dielectric material, annealing the GST material film, and forming a top electrode at an upper portion of the via.

Abstract: The present invention discloses a method including: providing a Group III-V component semiconductor material; forming a first layer over a surface of the Group III-V component semiconductor material, the first layer to unpin a Fermi level at the surface; forming a second layer over the first layer, the second layer for scaling an equivalent oxide thickness (EOT); and annealing the first layer before or after forming the second layer to remove bulk trap defects in the first layer.

Abstract: An electro-optic semiconductor package and fabrication method provides enhanced performance. An integrated circuit (IC) having one or more IC contact pads is provided, where the IC contact pads are connected to an IC on the IC wafer. An intermediate wafer having one or more intermediate contact pads is provided, where the intermediate contact pads are connected to an electro-optic arrangement on the intermediate wafer. The method further provides for direct copper bonding the IC contact pads to adjacent intermediate contact pads such that an electro-optic semiconductor package results.

Abstract: An optical grating is disposed on a waveguide to redirect light from the interior of the waveguide through the opposite side of the waveguide from the grating. In one embodiment the waveguide, the grating, and an optical sensor are combined in a single monolithic structure. In another embodiment, an absorbing layer is directly connected to the waveguide in the region of the grating. In still another embodiment, efficiency of the grating is improved by having a high index contrast between the refractive index of the grating and the refractive index of the cladding disposed over the grating, and by having an appropriately sized discontinuity in the grating.

Abstract: Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first gate is disposed laterally from the body and the second gate is disposed laterally from the first gate.

Abstract: Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first gate is disposed laterally from the body and the second gate is disposed laterally from the first gate. The horizontal member of the first gate overlaps the horizontal member of the second gate.

Abstract: A heteostructure having a first and a second layer, in micrometer or smaller (e.g. nanometer) scale, arranged in a configuration defining at least one undercut at one side of the second layer, underneath the first layer, is described herein. In various embodiments, the undercut is filled with passivation materials to protect the layers underneath the first layer. Further, in various embodiments, a large metal contact layer including coverage of the first layer sidewall may be employed to provide significant increase in contact area, and to reduce the device contact resist value.

Abstract: The present invention discloses a method including: providing a Group III-V component semiconductor material; forming a first layer over a surface of the Group III-V component semiconductor material, the first layer to unpin a Fermi level at the surface; forming a second layer over the first layer, the second layer for scaling an equivalent oxide thickness (EOT); and annealing the first layer before or after forming the second layer to remove bulk trap defects in the first layer.

Abstract: The present invention discloses a method including: providing a Group III-V component semiconductor material; forming a first layer over a surface of the Group III-V component semiconductor material, the first layer to unpin a Fermi level at the surface; forming a second layer over the first layer, the second layer for scaling an equivalent oxide thickness (EOT); and annealing the first layer before or after forming the second layer to remove bulk trap defects in the first layer.

Abstract: An electro-optic semiconductor package and fabrication method provides enhanced performance. An integrated circuit (IC) having one or more IC contact pads is provided, where the IC contact pads are connected to an IC on the IC wafer. An intermediate wafer having one or more intermediate contact pads is provided, where the intermediate contact pads are connected to an electro-optic arrangement on the intermediate wafer. The method further provides for direct copper bonding the IC contact pads to adjacent intermediate contact pads such that an electro-optic semiconductor package results.

Abstract: An electro-optic semiconductor package and fabrication method provides enhanced performance. An integrated circuit (IC) having one or more IC contact pads is provided, where the IC contact pads are connected to an IC on the IC wafer. An intermediate wafer having one or more intermediate contact pads is provided, where the intermediate contact pads are connected to an electro-optic arrangement on the intermediate wafer. The method further provides for direct copper bonding the IC contact pads to adjacent intermediate contact pads such that an electro-optic semiconductor package results.

Abstract: Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first gate is disposed laterally from the body and the second gate is disposed laterally from the first gate. The horizontal member of the first gate overlaps the horizontal member of the second gate.

Abstract: Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first gate is disposed laterally from the body and the second gate is disposed laterally from the first gate.

Abstract: Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first gate is disposed laterally from the body and the second gate is disposed laterally from the first gate. The horizontal member of the first gate overlaps the horizontal member of the second gate.

Abstract: Spin-orbital quantum cellular automata logic devices and integrated circuits in the form of a substrate having a thin film of material on the substrate having strongly coupled spin-orbital states, the thin film being patterned to define at least one input and at least one output, and to perform at least one logic operation by associated arrangement of the spin-orbital states between the input and the output. The logic devices and integrated circuits further include an input device at each input to define the spin-orbital states at each input, and an output sensor at each output for sensing the spin-orbital states of the thin film at the output. In an integrated circuit, the output of one gate or circuit, in the form of the ferromagnetically aligned spins, can be directly coupled to the next gate or circuit, so that entire circuits can be fabricated and effectively interconnected, only requiring interfacing for overall.

Abstract: An optical grating is disposed on a waveguide to redirect light from the interior of the waveguide through the opposite side of the waveguide from the grating. In one embodiment the waveguide, the grating, and an optical sensor are combined in a single monolithic structure. In another embodiment, an absorbing layer is directly connected to the waveguide in the region of the grating. In still another embodiment, efficiency of the grating is improved by having a high index contrast between the refractive index of the grating and the refractive index of the cladding disposed over the grating, and by having an appropriately sized discontinuity in the grating.

Abstract: An electro-optic semiconductor package and fabrication method provides enhanced performance. An integrated circuit (IC) having one or more IC contact pads is provided, where the IC contact pads are connected to an IC on the IC wafer. An intermediate wafer having one or more intermediate contact pads is provided, where the intermediate contact pads are connected to an electro-optic arrangement on the intermediate wafer. The method further provides for direct copper bonding the IC contact pads to adjacent intermediate contact pads such that an electro-optic semiconductor package results.

Abstract: An optical grating is disposed on a waveguide to redirect light from the interior of the waveguide through the opposite side of the waveguide from the grating. In one embodiment the waveguide, the grating, and an optical sensor are combined in a single monolithic structure. In another embodiment, an absorbing layer is directly connected to the waveguide in the region of the grating. In still another embodiment, efficiency of the grating is improved by having a high index contrast between the refractive index of the grating and the refractive index of the cladding disposed over the grating, and by having an appropriately sized discontinuity in the grating.

Abstract: Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first gate is disposed laterally from the body and the second gate is disposed laterally from the first gate. The horizontal member of the first gate overlaps the horizontal member of the second gate.

Abstract: An optical grating is disposed on a waveguide to redirect light from the interior of the waveguide through the opposite side of the waveguide from the grating. In one embodiment the waveguide, the grating, and an optical sensor are combined in a single monolithic structure. In another embodiment, an absorbing layer is directly connected to the waveguide in the region of the grating. In still another embodiment, efficiency of the grating is improved by having a high index contrast between the refractive index of the grating and the refractive index of the cladding disposed over the grating, and by having an appropriately sized discontinuity in the grating.